Graphic processing apparatus utilizing improved data transfer to reduce memory size

Abstract

A Memory Interface and Video Attribute Controller (MIVAC) is inserted between a dynamic RAM (DRAM) capable of a consecutive data read operation, such as the operation associated with the static column mode, page mode, or nibble mode, and a graphic processor to provide a parallel data processing. A serial data transfer is executed on each data bus between the MIVAC and the DRAM, whereas parallel data transfer is conducted between the MIVAC and the graphic processor. As a result, the graphic processor can be configured with a reduced number of DRAMs so that the graphic processor operates without paying attention to the consecutive data read mode of the DRAM.

1. A graphic processing apparatus comprising:
 memory means, including a plurality of memory locations in an array of columns, having corresponding column addresses, and rows, having corresponding row addresses, for storing data;    data processing means for specifying a row address in said memory means for retrieval of data from the memory locations at the different column addresses within the specified row of memory locations and processing of the retrieved data to generate graphic signals;    memory control means;    a memory data bus having m lines and interconnecting the memory means and the memory control means to transmit m bits of data in parallel therebetween, where m is an integer; and    a processor data bus having n lines and interconnecting the data processing means and the memory control means to transmit n bits of data in parallel therebetween, where n is an integer and n>m;    said memory control means including storage means for temporarily storing data received serially on said memory data bus from memory locations at different column addresses of the memory means row corresponding with the specified row address, and transmitting the temporarily stored data in parallel on said processor data bus to said data processing means for processing thereof to generate graphic signals.    
     
     
       2. A graphic processing apparatus comprising:
 memory means, including a plurality of memory locations in an array of columns, having corresponding column addresses, and rows, having corresponding row addresses, for storing data;    data processing means for specifying a row address in said memory means for writing of data in the memory locations at the different column addresses within the specified row of memory locations;    memory control means;    a memory data bus having m lines and interconnecting the memory means and the memory control means to transmit m bits of data in parallel therebetween, where m is an integer; and    a processor data bus having n lines and interconnecting the data processing means and the memory control means to transmit n bits of data in parallel therebetween, where n is an integer and n>m;    said memory control means including multiplexer means for multiplexing data received in parallel on said processor data bus into serial data and applying the serial data to said memory data bus for writing thereof in memory locations at different column addresses of the memory means row corresponding with the specified row address.    
     
     
       3. A graphic processing apparatus comprising:
 memory means, including a plurality of memory locations in an array of columns, having corresponding column addresses, and rows, having corresponding row addresses, for storing data;    data processing means for specifying a row address of memory locations in said memory means for transfer of a data word therewith;    memory control means;    a memory data bus having m lines and interconnecting the memory means and the memory control means to transmit m bits of data in parallel therebetween, where m is an integer; and    a processor data bus having n lines and interconnecting the data processing means and the memory control means to transmit n bits of data in parallel therebetween, where n is a multiple of m;    said memory control means including counter means, responsive to receipt on said processor data bus of a row address specified by said processor means to specify an n-bit data word in said memory means, for successively generating n column addresses, applying the received row address and m of the generated column addresses on said memory data bus to transfer data between said memory means and said data processor means, with the data transfer including transfer of m bits of data in parallel between said memory means and said memory control means, and transfer of n bits of data between said memory control means and said data processor means.    
     
     
       4. A graphic processing apparatus comprising:
 memory means, including a plurality of memory locations in an array of columns, having corresponding column addresses, and rows, having corresponding row addresses, for storing pixel information;    data processing means for specifying addresses of memory locations in said memory means for retrieval of pixel information therefrom and processing of the retrieved pixel information to generate graphic signals;    memory control means coupled to said memory means an said data processing means for retrieving pixel information from said memory means and applying the retrieved pixel information to said data processing means for processing thereof; and    output means connected to said memory control means for outputting processed pixel information to generate graphics.    
     
     
       5. A graphic processing apparatus as claimed in  claim 4 , wherein the pixel information comprises multi-bit pixel information units corresponding to one pixel. 
     
     
       6. A graphic processing apparatus as claimed in  claim 4 , wherein the pixel information comprises pixel information units, and wherein said memory control means includes means for selecting the number of bits in each pixel information unit. 
     
     
       7. A graphic processing apparatus as claimed in  claim 4 , wherein said memory control means includes storage means for temporarily storing pixel information retrieved from said memory means. 
     
     
       8. A graphic processing apparatus comprising:
 memory means, including a plurality of memory locations in an array of columns, having corresponding column addresses, and rows, having corresponding row addresses, for storing data;    data processing means for specifying a row address in said memory means for transfer of data between the data processing means and the memory locations at the different column addresses within the specified row of memory locations;    memory control means;    a memory data bus having m lines and interconnecting the memory means and the memory control means to transmit m bits of data in parallel therebetween, where m is an integer; and    a processor data bus having n lines and interconnecting the data processing means and the memory control means to transmit n bits of data in parallel therebetween, where n is an integer and n>m;    said memory control means including storage means for temporarily storing data received on said memory bus from memory locations at different column addresses of the memory location row corresponding with the specified row address and transmitting the temporarily stored data in parallel on said processor data bus to said data processing means for processing thereof, and multiplexer means for multiplexing data received in parallel on said processor data bus into serial data and applying the serial data to said serial memory data bus for writing thereof in memory locations at different column addresses of the memory location row corresponding with the specified row address.    
     
     
       9. A graphic processing apparatus comprising:
   a memory which stores graphic data;        a data processor which executes a predetermined graphic processing to generate graphic data to be stored in said memory;        a memory controller which controls data transfer between said memory and said data processor in accordance with a request from said data processor;        a digital to analog converter  ( DAC ) , connected to said memory controller, which outputs said graphic data read out from said memory;        a first bus, having m  ( wherein m is an integer )  bits width, connected between said memory and said memory controller, which transfers m bits of data in parallel; and        a second bus, having n  ( wherein n is an integer, n>m )  bits width, connected between said memory controller and said data processor, which transfers n bits of data in parallel;        wherein said memory controller comprises:      a storage which temporarily stores graphic data read out from said memory in successive groups of m bits of data during a predetermined period of time through said first bus,        a circuit which forms n bits of data using said successive groups of m bits of data and supplies said n bits of data in parallel to said data processor through said second bus based on an indication from said data processor, and          a converter which converts said graphic data temporarily stored in said storage into serial data which is provided to said DAC based on an indication from said data processor.     
     
     
       10. An apparatus according to  claim 9 , wherein said memory controller further comprises:
   a multiplexer which outputs the n bits graphic data transferred from said data processor to said first bus having m bits width in a time shared fashion.     
     
     
       11. An apparatus according to  claim 9 , wherein said memory controller further comprises:
   means for generating an address signal for accessing said memory plural times, in response to a signal for accessing said memory supplied from said data processor.     
     
     
       12. An apparatus according to  claim 9 , wherein graphic data to be transferred to said memory controller through said first bus is read out from said memory plural times within a unit transfer time in a time shared fashion, based on an access signal to said memory designated by said data processor. 
     
     
       13. An apparatus according to  claim 12 , wherein the graphic data transferred to said memory controller is supplied to said data processor through said second bus within a time longer than twice said unit transfer time. 
     
     
       14. A graphic processing apparatus comprising:
   a memory which stores graphic data;        a data processor which executes predetermined graphic processing to generate graphic data;        a memory controller which controls transfer of data between said memory and said data processor in response to a request from said data processor;        a digital to analog converter  ( DAC ) , connected to said memory controller, which outputs said graphic data read out from said memory;        a first bus having an m - bit width  ( wherein m is an integer )  and connected between said memory and said memory controller, which transfers data of m bits in parallel; and        a second bus having an n - bit width  ( wherein n is an integer and n>m )  and connected between said memory controller and said data processor, which transfers data of n bits in parallel;        wherein said memory controller concludes:      a storage which temporarily stores graphic data read out from said memory successively in a predetermined period of time via said first bus,        a circuit which applies said temporarily stored graphic data to said data processor as n - bit parallel data based on an indication from said data processor, and          a converter which converts said temporarily stored graphic data into serial data and outputs the serial data to said DCA based on an indication from said data processor.     
     
     
       15. A graphic processing apparatus according to  claim 14 , wherein said memory controller includes a multiplexer which outputs n- bit graphic data transferred from said data processor on said first bus having the m - bit width successively in a time - sharing manner.   
     
     
       16. A graphic processing apparatus according to  claim 15 , wherein said memory controller includes a second circuit which generates address signals for accessing said memory plural times with respect to a signal for accessing said memory means applied from said data processor. 
     
     
       17. A graphic processing apparatus according to  claim 15 , wherein graphic data to be transferred to said memory controller via said first bus are successively read out plural times within a transfer unit time in a predetermined period of time on the basis of an access signal to said memory designated by said data processor. 
     
     
       18. A graphic processing apparatus according to  claim 17 , wherein graphic data transferred to said memory controller are applied to said data processor via said second bus within a time period more than two times said transfer unit time. 
     
     
       19. A graphic processing apparatus according to  claim 14 , wherein said memory controller includes a second circuit which generates address signals for accessing said memory plural times with respect to a signal for accessing said memory applied from said data processor. 
     
     
       20. A graphic processing apparatus according to  claim 14 , wherein graphic data to be transferred to said memory controller via said first bus are successively read out plural times within a transfer unit time in a predetermined period of time on the basis of an access signal to said memory designated by said data processor. 
     
     
       21. A graphic processing apparatus according to  claim 20 , wherein graphic data transferred to said memory controller are applied to said data processor via said second bus within a time period more than two times said transfer unit time. 
     
     
       22. A graphic processing apparatus comprising:
   a memory which stores graphic data, said memory being accessed by using a row address and a column address;        a data processor which executes predetermined graphic processing to generate graphic data;        a memory controller which controls data transfer of data between said memory and said data processor in response to a request from said data processor;        a digital to analog converter  ( DAC ) , connected to said memory controller, which outputs said graphic data read out from said memory;        a first bus having an m - bit width  ( wherein m is an integer )  and connected between said memory and said memory controller, which transfers data of m bits in parallel; and        a second bus having an n - bit width  ( wherein n is an integer and n>m )  and connected between said memory controller and said data processor, which transfers data of n bits in parallel; and        wherein said memory controller includes:      a first circuit which reads out a plurality of graphic data at different column addresses at a same row address from said memory via said first bus successively in a predetermined period of time,        a second circuit which applies said read - out graphic data to said data processor as n - bit parallel data based on an indication from said data processor, and        a converter which converts said read - out graphic data into serial data and outputs the serial data to said DAC based on an indication from said data processor.       
     
     
       23. A graphic processing apparatus according to  claim 22 , wherein said memory controller includes a third circuit which successively generates a plurality of column addresses based on a signal for accessing said memory applied from said data processor. 
     
     
       24. A memory controller for controlling transference of data between a memory and a processor, said memory controller comprising:
   m bit terminals for coupling to said memory, wherein successive groups of m bits of data is transferred through said m bit terminals between said memory and said controller by performing plural read operations within a memory cycle  ( where m is an integer );      n bit terminals for coupling to said processor, wherein n bits of data is transferred in parallel through said n bit terminals between said controller and said processor  ( where n is an integer and n>m );      a storage which temporarily stores graphic data read out from said memory in successive groups of m bits of data during a predetermined period of time through said m bit terminals;        a first circuit which forms n bits of data by combining successive groups of m bits of data from said m bit terminals and supplies said n bits of data in parallel to said n bit terminals based on an indication from said processor; and        a converter which converts said graphic data temporarily stored in said storage into serial data which is supplied to a digital to analog converter  ( DAC ) , said DAC being connected to said memory controller.     
     
     
       25. A memory controller according to  claim 24 , wherein said successive groups of m bits of data from said m bit terminals are read out of said memory by performing plural read operations within a memory cycle based on an address specified by said processor. 
     
     
       26. A memory controller according to  claim 25 , wherein said n bits of data is applied to said processor through said n bit terminals in a unit of time more than two times said memory cycle. 
     
     
       27. A memory controller according to  claim 24 , wherein said successive groups of m bits of data each includes an m bit portion of said n bits of data. 
     
     
       28. A graphic processing apparatus comprising:
   a memory which stores graphic data;        a data processor which executes a predetermined graphic processing to generate graphic data to be stored in said memory;        a memory controller which controls data transfer between said memory and said data processor in accordance with a request from said data processor;        a first bus, having m  ( wherein m is an integer )  bits width, connected between said memory and said memory controller, which transfers m bits of data in parallel; and        a second bus, having n  ( wherein n is an integer, n>m )  bits width, connected between said memory controller and said data processor, which transfers n bits of data in parallel;        wherein said memory controller comprises:      at least one output terminal;        a storage which temporarily stores graphic data read out from said memory in successive groups of m bits of data during a predetermined period of time through said first bus,        a circuit which forms n bits of data using said successive groups of m bits of data and supplies said n bits of data in parallel to said data processor through said second bus based on an indication from said data processor, and        a converter which converts said graphic data temporarily stored in said storage into serial data which is provided to said at least one output terminal based on an indication from said data processor.       
     
     
       29. An apparatus according to  claim 28 , wherein said memory controller further comprises:
   a multiplexer which outputs the n bits graphic data transferred from said data processor to said first bus having m bits width in a time shared fashion.     
     
     
       30. An apparatus according to  claim 28 , wherein said memory controller further comprises:
   a second circuit which generates an address signal for accessing said memory plural times, in response to a signal for accessing said memory supplied from said data processor.     
     
     
       31. An apparatus according to  claim 28 , wherein graphic data to be transferred to said memory controller through said first bus is read out from said memory plural times within a unit transfer time in a time shared fashion, based on an access signal to said memory designated by said data processor. 
     
     
       32. An apparatus according to  claim 31 , wherein the graphic data transferred to said memory controller is supplied to said data processor through said second bus within a time longer than twice said unit transfer time. 
     
     
       33. A graphic processing apparatus comprising:
   a memory which stores graphic data;        a data processor which executes predetermined graphic processing to generate graphic data;        a memory controller which controls transfer of data between said memory and said data processor in response to a request from said data processor;        a first bus having an m - bit width  ( wherein m is an integer )  and connected between said memory and said memory controller, which transfers data of m bits in parallel; and        a second bus having an n - bit width  ( wherein n is an integer and n>m )  and connected between said memory controller and said data processor, which transfers data of n bits in parallel,        wherein said memory controller includes:      at least one output terminal;        a storage which temporarily stores graphic data read out from said memory successively in a predetermined period of time via said first bus,        a circuit which applies said temporarily stored graphic data to said data processor as n - bit parallel data based on an indication from said data processor, and        a converter which converts said temporarily stored graphic data into serial data and outputs the serial data to said at least one output terminal based on an indication from said data processor.       
     
     
       34. A graphic processing apparatus according to  claim 33 , wherein said memory controller includes a multiplexer which outputs n- bit graphic data transferred from said data processor on said first bus having the m - bit width successively in a time - sharing manner.   
     
     
       35. A graphic processing apparatus according to  claim 34 , wherein said memory controller includes a second circuit which generates address signals for accessing said memory plural times with respect to a signal for accessing said memory means applied from said data processor. 
     
     
       36. A graphic processing apparatus according to  claim 34 , wherein graphic data to be transferred to said memory controller via said first bus are successively read out plural times within a transfer unit time in a predetermined period of time on the basis of an access signal to said memory designated by said data processor. 
     
     
       37. A graphic processing apparatus according to  claim 36 , wherein graphic data transferred to said memory controller are applied to said data processor via said second bus within a time period more than two times said transfer unit time. 
     
     
       38. A graphic processing apparatus according to  claim 33 , wherein said memory controller includes a second circuit which generates address signals for accessing said memory plural times with respect to a signal for accessing said memory applied from said data processor. 
     
     
       39. A graphic processing apparatus according to  claim 33 , wherein graphic data to be transferred to said memory controller via said first bus are successively read out plural times within a transfer unit time in a predetermined period of time on the basis of an access signal to said memory designated by said data processor. 
     
     
       40. A graphic processing apparatus according to  claim 39 , wherein graphic data transferred to said memory controller are applied to said data processor via said second bus within a time period more than two times said transfer unit time. 
     
     
       41. A graphic processing apparatus comprising:
   a memory which stores graphic data, said memory being accessed by using a row address and a column address;        a data processor which executes predetermined graphic processing to generate graphic data;        a memory controller which controls transfer of data between said memory and said data processor in response to a request from said data processor;        a first bus having an m - bit width  ( wherein m is an integer )  and connected between said memory and said memory controller, which transfers data of m bits in parallel; and        a second bus having an n - bit width  ( wherein n is an integer and n>m )  and connected between said memory controller and said data processor, which transfers data of n bits in parallel; and        wherein said memory controller includes:      at least one output terminal;        a first circuit which reads out a plurality of graphic data at different column addresses at a same row address from said memory via said first bus successively in a predetermined period of time,        a second circuit which applies said read - out graphic data to said data processor as n - bit parallel data based on an indication from said data processor, and        a converter which converts said read - out graphic data into serial data and outputs the serial data to said at least one output terminal based on an indication from said data processor.       
     
     
       42. A graphic processing apparatus according to  claim 41 , wherein said memory controller includes a third circuit which successively generates a plurality of column addresses based a signal for accessing said memory applied from said data processor. 
     
     
       43. A memory controller for controlling transference of data between a memory and a processor, said memory controller comprising:
   m bit terminals for coupling to said memory, wherein successive groups of m bits of data is transferred through said m bit terminals between said memory and said controller by performing plural read operations within a memory cycle  ( where m is an integer );      n bit terminals for coupling to said processor, wherein n bits of data is transferred in parallel through said n bit terminals between said controller and said processor  ( where n is an integer and n>m );      a storage which temporarily stores graphic data read out from said memory in successive groups of m bits of data during a predetermined period of time through said m bit terminals;        a first circuit which forms n bits of data by combining successive groups of m bits of data from said m bit terminals and supplies said n bits of data in parallel to said n bit terminals based on an indication from said processor; and        a converter which converts said graphic data temporarily stored in said storage into serial data which is supplied to at least one output terminal, said at least one output terminal being connected to said memory controller.     
     
     
       44. A memory controller according to  claim 43 , wherein said successive groups of m bits of data from said m bit terminals are read out of said memory by performing plural read operations within a memory cycle based on an address specified by said processor. 
     
     
       45. A memory controller according to  claim 44 , wherein said n bits of data is applied to said processor through said n bit terminals in a unit of time more than two times said memory cycle. 
     
     
       46. A memory controller according to  claim 43 , wherein said successive groups of m bits of data each includes an m bit portion of said n bits of data.