Semiconductor integrated circuit arrangement fabrication method

Abstract

To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable state in a plasma and a flon gas to interact with each other and selectively obtaining desired dissociated species.

1. An integrated circuit device fabrication method, comprising the following steps:
 (a) forming a silicon nitride film over a major surface of a wafer; which major surface has a gate structure including a gate electrode and a gate protecting insulation covering side and upper surface of the gate electrode, and an isolation region including a recess region and an isolating insulation therein;    (b) forming a silicon oxide film over the silicon nitride film;    (c) forming a patterned masking film over the silicon oxide film;    (d) forming a hole in the silicon oxide film by dry-etching the silicon oxide film using the nitride film as an etching stopper with a cyclic perfluorocarbon gas with three or more carbon atoms under the condition that the patterned masking film exists over the silicon oxide film and an inert gas component occupies no less than 50% of a first gas ambiance around the wafer, thereby exposing the silicon nitride film at the bottom of the hole; and then    (e) removing the silicon nitride film at the bottom of the hole by etching the silicon nitride film, thereby exposing the major surface of the wafer at the bottom of the hole between the gate structure and the isolation region.    
     
     
       2. An integrated circuit device fabrication method according to  claim 1 , wherein the inert gas component that occupies no less than 50% of the first gas ambiance around the wafer is an argon gas. 
     
     
       3. An integrated circuit device fabrication method according to  claim 1 , wherein the inert gas component occupies no less than 80% of the first gas ambiance around the wafer, and wherein the inert gas component is an argon gas. 
     
     
       4. An integrated circuit device fabrication method according to  claim 3 , wherein the cyclic perfluorocarbon gas includes C 4 F 8 . 
     
     
       5. An integrated circuit device fabrication method according to  claim 3 , wherein the removal of the silicon nitride film at the bottom of the hole is performed by a dry-etching. 
     
     
       6. An integrated circuit device fabrication method according to  claim 3 , wherein the removal of the silicon nitride film at the bottom of the hole is performed by a dry-etching with a non-cyclic fluorocarbon gas, under the condition that the proportion of an inert gas component occupies no less than 80% of a second gas ambiance around the wafer. 
     
     
       7. An integrated circuit device fabrication method according to  claim 6 , wherein the inert gas component that occupies no less than 80% of the second gas ambiance around the wafer is an argon gas. 
     
     
       8. An integrated circuit device fabrication method according to  claim 7 , wherein the non-cyclic fluorocarbon gas includes a carbon gas with one carbon atom. 
     
     
       9. An integrated circuit device fabrication method according to  claim 8 , wherein the non-cyclic fluorocarbon gas is CH 2 F 2 . 
     
     
       10. An integrated circuit device fabrication method, comprising the steps of:
 ( a )  forming a silicon nitride film over a major surface of a wafer having a first and second gate electrode adjacent to each other;      ( b )  forming a silicon oxide film over the silicon nitride film;      ( c )  forming a patterned masking film over the silicon oxide film;      ( d )  forming a hole in the silicon oxide film by ion assist dry etching the silicon oxide film with using the silicon nitride film as an etching stopper with a first etching gas that includes an inert gas component and a first perfluorocarbon reaction gas component with three or more carbon atoms under the condition that the patterned masking film exists over the silicon oxide film and the proportion of the inert gas component is not less than  80   %  of a gas ambience around the wafer, thereby exposing the silicon nitride film at the bottom of the hole; and      ( e )  extending the hole down to an underlying layer of the silicon nitride between the first and second gate electrodes by dry - etching the silicon nitride film with a second etching gas including a reaction gas component different from the first perfluorocarbon reaction gas component.     
     
     
       11. An integrated circuit device fabrication method according to  claim 10 , wherein the inert gas component of the first etching gas includes an argon gas. 
     
     
       12. An integrated circuit device fabrication method according to  claim 11 , wherein the first perfluorocarbon reaction gas component includes a chain compound type perfluorocarbon gas. 
     
     
       13. An integrated circuit device fabrication method according to  claim 11 , wherein the reaction gas component of the second etching gas contains a fluorocarbon gas with one carbon atom. 
     
     
       14. An integrated circuit device fabrication method according to  claim 13 , wherein the fluorocarbon gas with one carbon atom is a hydrogen- containing fluorocarbon gas.   
     
     
       15. An integrated circuit device fabrication method according to  claim 14 , wherein the second etching gas includes an inert gas component. 
     
     
       16. An integrated circuit device fabrication method according to  claim 15 , wherein a space between the first and second gate electrodes is  0 . 25  μm or less. 
     
     
       17. An integrated circuit device fabrication method according to  claim 16 , wherein a size of an opening of the patterned masking film corresponding to the hole is  0 . 3  μm or less. 
     
     
       18. An integrated circuit device fabrication method according to  claim 11 , wherein the first perfluorocarbon reaction gas component includes a cyclic compound type perfluorocarbon gas. 
     
     
       19. An integrated circuit device fabrication method according to  claim 17 , wherein the patterned masking film is a photoresist film. 
     
     
       20. An integrated circuit device fabrication method according to  claim 11 , wherein the silicon oxide film is a borophosphosilicate glass film. 
     
     
       21. An integrated circuit device fabrication method according to  claim 11 , wherein the first perfluorocarbon reaction gas with one carbon atom is C 4   F   8 . 
     
     
       22. An integrated circuit device fabrication method according to  claim 17 , wherein the fluorocarbon reaction gas with one carbon atom is CH 2   F   2 . 
     
     
       23. An integrated circuit device fabrication method according to  claim 17 , wherein the hole is a contact hole. 
     
     
       24. An integrated circuit device fabrication method, comprising the steps of:
 ( a )  forming a silicon nitride film over a major surface of a wafer having a gate electrode and an isolation region adjacent to each other;      ( b )  forming a silicon oxide film over the silicon nitride film;      ( c )  forming a patterned masking film over the silicon oxide film;      ( d )  forming a hole in the silicon oxide film by ion assist dry etching the silicon oxide film with using the silicon nitride film as an etching stopper with a first etching gas that includes an inert gas component and a first perfluorocarbon reaction gas component with three or more carbon atoms under the condition that the patterned masking film exists over the silicon oxide film and the proportion of the inert gas component is not less than  80   %  of a gas ambience around the wafer, thereby exposing the silicon nitride film at the bottom of the hole; and      ( e )  extending the hole down to an underlying layer of the silicon nitride between the gate electrode and the isolation region by dry - etching the silicon nitride film with a second etching gas including a reaction gas component different from the first perfluorocarbon reaction gas component.     
     
     
       25. An integrated circuit device fabrication method according to  claim 24 , wherein the inert gas component of the first etching gas includes an argon gas. 
     
     
       26. An integrated circuit device fabrication method according to  claim 23 , wherein the first perfluorocarbon reaction gas component includes a chain compound type perfluorocarbon gas. 
     
     
       27. An integrated circuit device fabrication method according to  claim 25 , wherein the reaction gas component of the second etching gas contains a fluorocarbon gas with one carbon atom. 
     
     
       28. An integrated circuit device fabrication method according to  claim 27 , wherein the fluorocarbon gas with one carbon atom is a hydrogen- containing fluorocarbon gas, and the second etching gas includes an inert gas component.   
     
     
       29. An integrated circuit device fabrication method according to  claim 28 , wherein a size of an opening of the patterned masking film corresponding to the hole is  0 . 3  μm or less. 
     
     
       30. An integrated circuit device fabrication method according to  claim 25 , wherein the first perfluorocarbon reaction gas component includes a cyclic compound typed perfluorocarbon gas. 
     
     
       31. An integrated circuit device fabrication method according to  claim 29 , wherein the patterned masking film is a photoresist film. 
     
     
       32. An integrated circuit device fabrication method according to  claim 25 , wherein the silicon oxide film is a borophosphosilicate glass film. 
     
     
       33. An integrated circuit device fabrication method according to  claim 29 , wherein the first perfluorocarbon reaction gas with one carbon atom is C 4   F   8 . 
     
     
       34. An integrated circuit device fabrication method according to  claim 29 , wherein the fluorocarbon reaction gas with one carbon atom is CH 2   F   2 . 
     
     
       35. An integrated circuit device fabrication method according to  claim 29 , wherein the hole is a contact hole.