Latch-up recovery in quantized feedback DC restorer circuits

Abstract

A method and apparatus for avoiding and or recovering from the latch-up condition in a quantized feedback DC restorer circuit for use in a digital data communication system receiver. An automatic gain control (AGC) circuit controls the level of the received data by comparing the AGC output with a quantized output signal from the DC restorer. A carrier detect circuit detects the presence of data transitions in the quantized output signal, and in the absence of such transitions continuously ramps up the gain of the AGC until such transitions are detected. The carrier detect circuit can be further used to disable, either entirely or partially, the positive feedback path of the DC restorer in the absence of transition in the quantized output signal. The present invention further provides an inherent muting function of the DC restorer output signal in the absence of valid data transitions.

1. A circuit for receiving an input signal and providing a quantized output signal in response, said quantized output signal being at either a first level or a second level, and said input signal being substantially at either said first level or said second level, said circuit comprising:
 (a) an automatic gain control (AGC) circuit for providing a gain signal which processes said input signal to output a controlled signal having a constant amplitude at either said first level or said second level, said AGC circuit being operative in a first mode to provide said gain signal in response to the difference between the level of said controlled signal and the level of said quantized output signal;    (b) a restorer circuit coupled to said AGC circuit for receiving said controlled signal and for providing said quantized output signal in response;    (c) a carrier detect circuit coupled to said AGC circuit and having an input for receiving said quantized output signal, said carrier detect circuit providing a detection signal for indicating the presence of a transition in the level of said quantized output signal, said detection signal being coupled to said AGC circuit;    
       such that during periods when said detection signal indicates that there are transitions in the level of said quantized output signal, said AGC circuit is operative in said first mode, and during periods when said detection signal indicates that there are no transitions in the level of said quantized output signal, said AGC circuit is operative in a second mode wherein said gate signal is continually increased, at least to a predetermined level. 
     
     
       2. A circuit according to  claim 1  wherein when said AGC circuit is operative in said second mode, said gain signal increases in a substantially linear manner until said gain value reaches said predetermined level. 
     
     
       3. A circuit according to  claim 2  wherein said predetermined level corresponds to a gain saturation level of said AGC circuit. 
     
     
       4. A circuit according to  claim 1  wherein said restorer circuit comprises:
 (a) a high-pass filter circuit for receiving said controlled signal and providing a high-pass filtered controlled signal in response;    (b) a low-pass filter circuit for receiving said quantized output signal and providing a low-pass filtered quantized output signal in response, said low pass filter circuit providing a feedback path for said low-pass filtered quantized output signal;    (c) a summer for adding said high-pass filtered controlled signal with said low-pass filtered quantized output signal to provide a slicer input signal; and    (d) a slicer circuit for comparing said slicer input signal to a slicer reference signal and providing said quantized output signal at a slicer output terminal in response.    
     
     
       5. A circuit according to  claim 4  wherein the time constant of said high pass circuit and the time constant of said low pass circuit are equal. 
     
     
       6. A circuit according to  claim 5  wherein the voltage swing of said controlled signal and the voltage swing of said quantized output signal are equal. 
     
     
       7. A circuit according to  claim 4  wherein said low pass filter circuit includes a disabling circuit responsive to said detection signal or a version thereof, so that said disabling circuit disables said feedback path during periods when said detection signal indicates that there are no transitions in the level of said quantized output signal. 
     
     
       8. A circuit according to  claim 7  wherein said disabling circuit comprises a feedback enable switch coupled between said slicer output terminal and said summer, said switch being operative in an open or closed position in response to said detection signal or a version thereof. 
     
     
       9. A circuit according to  claim 4  wherein said low pass filter circuit includes a disabling circuit responsive to said detection signal or a version thereof, so that said disabling circuit partially disables said feedback path during periods when said detection signal indicates that there are no transitions in the level of said quantized output signal. 
     
     
       10. A circuit according to  claim 9  wherein said disabling circuit comprises a feedback control amplifier coupled between said slicer output terminal and said summer, said feedback control amplifier having a feedback control gain with a value in the range of 0 to 1, said value corresponding to the extent that said feedback path may be partially disabled, said disabling circuit further comprising a feedback enable switch being operative, in response to said detection signal or a version thereof, in a first position to insert said feedback control amplifier in said feedback path and in a second position to bypass said feedback control amplifier in said feedback path. 
     
     
       11. A circuit according to  claim 10  wherein said feedback control gain value is changeable. 
     
     
       12. A circuit according to  claim 1 ,  7 , or  9  wherein said carrier detect circuit comprises:
 (a) a high-pass filter circuit for receiving said quantized output signal and providing a high pass filtered quantized output signal in response;    (b) a peak detector circuit for receiving said high pass filtered quantized output signal and providing a peak signal representative of the peak amplitude of said high pass filtered quantized output signal in response; and    (c) a comparator circuit for comparing said peak signal to a carrier detect threshold signal and outputting said detection signal in response.    
     
     
       13. A method for avoiding a latch-up condition in the output of a digital data communication receiver which receives an input signal and provides a quantized output signal in response, said quantized output signal being at either a first level or a second level, and said input signal being substantially at either said first level or said second level, said receiver comprising an automatic gain control circuit, a quantized feedback DC restorer circuit, and a carrier detect circuit, said method comprising the steps of:
 (a) processing the input signal in response to a gain signal to provide a controlled signal having a constant amplitude at either said first level or said second level, said gain signal being responsive in a first manner to the difference between the level of said controlled signal and the level of said quantized output signal;    (b) restoring the DC and low frequency components of said controlled signal to provide a quantized output signal; and    (c) detecting the presence of a transition in the level of said quantized output signal;    
       such that during periods when there are transitions in the level of said quantized output signal, said gain signal is responsive in said first manner, and during periods when there are no transitions in the level of said quantized output signal, said gain signal is responsive in a second manner wherein said gain signal continually increases to at least a predetermined value. 
     
     
       14. A method according to  claim 13  wherein when said gain signal is responsive in said second manner, said gain signal increases substantially linearly until said gain signal reaches said predetermined value. 
     
     
       15. A method according to  claim 14  wherein step (b) further comprises the steps of:
 high-pass filtering said controlled signal to provide a high-pass filtered controlled signal;    low-pass filtering said quantized output signal to provide a low-pass filtered quantized output signal;    adding said low-pass filtered quantized output signal to said high-pass filtered controlled signal to provide a slicer input signal; and    comparing said slicer input signal a slicer reference signal and providing said quantized output signal in response.    
     
     
       16. A method according to  claim 15  wherein said step of low-pass filtering is disabled during periods when said detection signal indicates that there are no transitions in the level of said quantized output signal. 
     
     
       17. A method according to  claim 15  wherein said step of low-pass filtering is partially disabled during periods when said detection signal indicates that there are no transitions in the level of said quantized output signal. 
     
     
       18. A circuit for receiving an input signal and providing a quantized output signal in response, said circuit comprising:
 ( a )  an amplifier for providing a controlled signal in response to said input signal and a gain signal;      ( b )  a restorer circuit coupled to said amplifier, said restorer circuit including an internal feedback path;      ( c )  a carrier detect circuit having an input for receiving said quantized output signal, said carrier detect circuit providing a first detection signal and a second detection signal for indicating the presence of a transition in the level of said quantized output signal;      ( d )  an automatic gain control  ( AGC )  circuit coupled to said amplifier, said restorer circuit and said carrier detect circuit for providing said gain signal in response to said controlled signal, said quantized output signal and said first detection signal; and      ( e )  a feedback disabling circuit coupled to said carrier detect circuit and said restorer circuit for controllably enabling and disabling said internal feedback path in response to said second detection signal.     
     
     
       19. A circuit according to  claim 18 , wherein said restorer circuit comprises:
 ( i )  a high - pass filter circuit for receiving said controlled signal and providing a high - pass filtered controlled signal in response;      ( ii )  a low - pass filter circuit for receiving said quantized output signal and providing a low - pass filtered quantized output signal in response, said low - pass filter circuit providing said internal feedback path for said low - pass filtered quantized output signal;      ( iii )  a summer for adding said high - pass filtered controlled signal with said low - pass filtered quantized output signal to provide a slicer input signal; and      ( iv )  a slicer circuit for comparing said slicer input signal to a slicer reference signal and providing said quantized output signal at a slicer output terminal in response.     
     
     
       20. A circuit according to  claim 19 , wherein the time constant of said high- pass filter circuit and the time constant of said low - pass filter circuit are equal.   
     
     
       21. A circuit according to  claim 20 , wherein said feedback disabling circuit includes a switch coupled between said slicer circuit and said summer, said switch having a first state and a second state, wherein in said first state, said switch is fully open to disable said internal feedback path and wherein in said second state, said switch is fully closed to enable said internal feedback path. 
     
     
       22. A circuit according to  claim 21 , wherein said switch is in said first state when said second detection signal does not indicate the presence of a transition and is in said second state when said second detection signal indicates the presence of a transition. 
     
     
       23. A circuit according to  claim 20 , wherein said feedback disabling circuit includes a feedback control amplifier coupled between said slicer circuit and said summer, said feedback control amplifier having a gain between  0  and  1 , wherein said gain corresponds to the extent to which said internal feedback path is enabled. 
     
     
       24. A circuit according to  claim 23 , wherein said feedback disabling circuit further includes a switch coupled between said slicer output and said summer, said switch being coupled in parallel with said feedback control amplifier, said switch having a first state and a second state, wherein in said first state, said switch inserts said feedback control amplifier into said internal feedback path and wherein in said second state, said switch bypasses said feedback control amplifier from said internal feedback path. 
     
     
       25. A circuit according to  claim 24 , wherein said switch is in said first state when said second detection signal does not indicate the presence of a transition and is in said second state when said second detection signal indicates the presence of a transition. 
     
     
       26. A circuit according to any one of claims  23 ,  24  or  25 , wherein said gain of said feedback control amplifier may be varied. 
     
     
       27. A circuit according to  claim 18 , wherein said first detection signal and said second detection signal are identical. 
     
     
       28. A circuit according to  claim 18 , wherein said second detection signal is a version of said first detection signal. 
     
     
       29. A circuit according to  claim 18 , wherein said AGC may be operative in a first mode when said first detection signal indicates that there is a transition in the level of said quantized output signal or in a second mode when said first detection signal indicates that there is no transition in the level of said quantized output signal, and wherein in said first mode, said gain signal corresponds to a difference between said controlled signal and said quantized output signal and wherein in said second mode said gain signal is continually increased, at least to a predetermined level. 
     
     
       30. A circuit according to  claim 29 , wherein said quantized output signal may be at either a first level or a second level and wherein said input signal is generally at either said first level or said second level. 
     
     
       31. A circuit according to  claim 29 , wherein when said AGC circuit is in said second mode, said gain signal increases in a substantially linear manner until said gain value reaches said predetermined level. 
     
     
       32. A circuit according to  claim 29 , wherein said predetermined level corresponds to a gain saturation level of said AGC circuit. 
     
     
       33. A circuit according to  claim 29 , wherein the voltage swing of said controlled signal and the voltage swing of said quantized output signal are equal. 
     
     
       34. A circuit according to  claim 18  or  29  wherein said carrier detect circuit comprises:
 ( a )  a high - pass filter circuit for receiving said quantized output signal and providing a high pass filtered quantized output signal in response;      ( b )  a peak detector circuit for receiving said high pass filtered quantized output signal and providing a peak signal representative of the peak amplitude of said high pass filtered quantized output signal in response; and      ( c )  a comparator circuit for comparing said peak signal to a carrier detect threshold signal and outputting said detection signal in response.     
     
     
       35. A method for avoiding a latch- up condition in the output of a digital data communication receiver which receives an input signal and provides a quantized output signal in response, said quantized output signal being at either a first level or a second level, and said input signal being substantially at either said first level or said second level, said receiver comprising an automatic gain control circuit, a quantized feedback DC restorer circuit, a carrier detect circuit, and a feedback disabling circuit, said method comprising:    ( a )  processing the input signal in response to a gain signal to provide a controlled signal having a constant amplitude at either said first level or said second level, said gain signal being responsive in a first manner to the difference between the level of said controlled signal and the level of said quantized output signal;      ( b )  selectively restoring the DC and low frequency components of said controlled signal to provide said quantized output signal by isolating said DC and low frequency components in said quantized output signal and summing said isolated DC and low frequency components into said controlled signal or a version thereof through a feedback path which may be controllably enabled or disabled; and      ( c )  detecting the presence of a transition in the level of said quantized output signal,      
       
         such that during periods when there are transitions in the level of said quantized output signal, said gain signal is responsive in said first manner and said feedback path is enabled, and during periods when there are no transitions in the level of said quantized output signal, said gain signal is responsive in a second manner wherein said gain signal continually increases to at least a predetermined value and said feedback path is at least partially disabled. 
       
     
     
       36. A method according to  claim 35 , wherein step ( b )  is accomplished by:    ( i )  high - pass filtering said controlled signal to provide a high pass filtered controlled signal;      ( ii )  selectively low - pass filtering said quantized output signal through said feedback path to provide a low - pass filtered quantized output signal,      ( iii )  adding said low - pass filtered quantized output signal to said high - pass filtered controlled signal to provide a slicer input signal; and      ( iv )  comparing said slicer input signal to a slicer reference signal and providing said quantized output signal in response.     
     
     
       37. A method according to  claim 36 , wherein when said gain signal is responsive in said second manner, said gain signal increases substantially linearly until said gain signal reaches said predetermined value. 
     
     
       38. A method according to  claim 36 , wherein said feedback path is partially disabled during periods when said detection signal indicates that there are no transitions in the level of said quantized output signal. 
     
     
       39. A method according to  claim 36 , wherein said feedback path is completely disabled during periods when said detection signal indicates that there are no transitions in the level of said quantized output signal.