System and method for providing an integrated circuit with a unique identification

Abstract

An integrated circuit identification device (ICID) to be incorporated into an integrated circuit (IC) includes an array of electronic cells in which the magnitude of an output signal of each cell is a function of randomly occurring parametric variations which vary from cell-to-cell. The ICID also includes a circuit for measuring the output of each cell and for producing output data having a value reflecting the particular combination of measured characteristics of all of the elements of the array. When we make the number of elements in the array large enough, we insure that to a high degree of probability, the pattern of measured array cell characteristics for an ICID embedded in any one IC will be unique and distinguishable from such patterns measured by ICIDs embedded in millions of other ICs. Thus the value of the output data produced by an ICID circuit acts as a unique “fingerprint” for the IC in which it is installed, and can be used as a unique identification (ID) for that IC.

1. An apparatus (ICID) installed on an integrated circuit (IC) for generating an identification number (ID) identifying the IC in which it is installed, the apparatus comprising:
 a plurality of identification cells formed within said IC, each having an output that is a substantial function of random parametric variations in said IC; and  
 measurement means for monitoring the output of said plurality of identification cells and for generating said ID in response thereto, wherein said ID is also a substantial function of random parametric variations in said cells.  
 
     
     
       2. The apparatus in accordance with  claim 1  wherein said measurement means establishes a value of said ID in accordance with the output of each of said plurality of identification cells. 
     
     
       3. The apparatus in accordance with  claim 2  wherein each of said identification cells comprises at least one transistor, and wherein the output of each cell is a function of an operating characteristic of that transistor that is in turn a function of said random parametric variations in said IC. 
     
     
       4. The apparatus in accordance with  claim 2  wherein each of said identification cells comprises two transistors having a difference in operating characteristics resulting from said random parametric variations in said IC, and wherein said output of said cell is a function of said difference in operating characteristics. 
     
     
       5. The apparatus in accordance with  claim 4  wherein said transistors are metal oxide semiconductor field effect transistors (MOSFETs). 
     
     
       6. The apparatus in accordance with  claim 2  further comprising a plurality of type cells formed within said IC, each type cell having an output that is substantially independent of said random parametric variations,
 wherein said measurement means also monitors the output of each of said plurality of type cells and also generates said ID in response to said output of each of said plurality of said type cells.  
 
     
     
       7. The apparatus in accordance with  claim 6  wherein said ID generated by said measurement means includes a first field reflecting a pattern of monitored outputs of said plurality of identification cells and a second field reflecting a pattern of monitored outputs of said plurality of type cells. 
     
     
       8. The apparatus in accordance with  claim 1  wherein said measurement means comprises:
 means for sequentially comparing magnitudes of monitored outputs of said identification cells and for generating a sequence of bits, each bit of said sequence indicating a result of a comparator of outputs of said identification cells; and  
 means for generating said ID in response to said sequence of bits.  
 
     
     
       9. The apparatus in accordance with  claim 1  wherein the output of each of said cells comprises two output signals that are functions of said random parametric variations, and wherein said output monitored by said measurement means comprises a difference between said two output signals. 
     
     
       10. The apparatus in accordance with  claim 9  wherein said measurement means comprises:
 means for performing comparisons of said differences between output signals of successive ones of said identification cells and for generating a sequence of bits, each bit of said sequence indicating a result of a separate one of said comparisons; and  
 means for generating said ID In response to said sequence of bits.  
 
     
     
       11. A method for providing an integrated circuit (IC) with an identification number (ID), the method comprising the steps of:
 forming a plurality of identification cells within said IC, each having an output that is a substantial function of random parametric variations in said IC; and  
 generating said ID in response to the output of each cell, wherein said ID is also a substantial function of random parametric variations in said IC.  
 
     
     
       12. The method in accordance with  claim 11  wherein a value of said ID is established in response to the output of each of said plurality of identification cells. 
     
     
       13. The method in accordance with  claim 12  wherein each of said identification cells comprises at least one transistor, and wherein said output is a function of an operating characteristic of that transistor that is in turn a function of said random parametric variations in said IC. 
     
     
       14. The method in accordance with  claim 12  wherein each of said identification cells comprises two transistors having a difference in operating characteristics resulting from said random variations in said IC, and wherein said output is a function of said difference between said operating characteristics of said transistors. 
     
     
       15. The method in accordance with  claim 14  wherein said transistors are metal oxide semiconductor field effect transistors (MOSFETs). 
     
     
       16. The method in accordance with  claim 11  wherein the step of generating said ID in response to the outputs comprises the substeps of:
 performing comparisons of the outputs of pairs of said identification cells;  
 generating a sequence of bits, each bit of said sequence indicating a result of a separate one of said comparisons; and  
 generating said ID in response to said sequence of bits.  
 
     
     
       17. The method in accordance with  claim 11  wherein each of said cells produces two output signals that are functions of said random parametric variations, and wherein said output of each cell comprises a difference between said two output signals. 
     
     
       18. The method in accordance with  claim 17  wherein the step of generating said ID in response to the output comprises the substeps of:
 performing comparisons of the outputs of pairs of said identification cells;  
 generating a sequence of bits, each bit of said sequence indicating a result of a separate one of said comparisons; and  
 generating said ID in response to said sequence of bits.  
 
     
     
       19. A method for providing an integrated circuit (IC) with an identification number (ID), the method comprising the steps of:
 forming a plurality of identification cells within said IC, each having an output that is substantially a function of random parametric variations in said IC;  
 forming a plurality of type cells within said IC, each type cell having an output that is substantially independent of said random parametric variations, and  
 generating said ID in response to a combination of the outputs of said plurality of identification cells and said plurality of type cells, wherein a value of said ID is established in accordance with the outputs of said plurality of identification cells and said plurality of type cells, and wherein said value is substantially a function of random parametric variations in said IC.  
 
     
     
       20. The method in accordance with  claim 19  wherein the generated ID includes a first field reflecting a pattern of the outputs of said plurality of identification cells and a second field reflecting a pattern of the outputs of said plurality of type cells. 
     
     
       21. An apparatus in an integrated circuit ( IC )  for generating an identification number  ( ID )  identifying the IC, the apparatus comprising:      an identification circuit formed within the IC, the identification circuit outputting signals that are a substantial function of random parametric variations in the IC; and        a measurement circuit, the measurement circuit receiving the signals that are a substantial function of random parametric variations in the IC, wherein the measurement circuit generates the ID, wherein the ID is a substantial function of the random parametric variations.      
     
     
       22. A method for providing an integrated circuit ( IC )  with an identification number  ( ID ) , the method comprising the steps of:      forming an identification circuit within the IC, the identification circuit outputting signals that are a substantial function of random parametric variations in the IC; and        generating the ID in response to the signals that are a substantial function of random parametric variations in the IC, wherein the ID is a substantial function of the random parametric variations.      
     
     
       23. A method for providing an integrated circuit ( IC )  with an identification number  ( ID ) , the method comprising the steps of:      forming an identification circuit within the IC, the identification circuit outputting signals that are substantially a function of random parametric variations in the IC;        forming a common value circuit within the IC, the common value circuit having an output that is substantially independent of the random parametric variations; and        generating the ID in response to the outputs of the identification circuit and the common value circuit, wherein the ID is substantially a function of the random parametric variations in the IC.      
     
     
       24. A method for identifying an integrated circuit ( IC ) , the method comprising the steps of:      manufacturing the IC as a batch process, wherein the IC is manufactured as one of a plurality of ICs by the batch process, wherein each of the ICs includes a plurality of identification cells each having an output that is a substantial function of random parametric variations in the particular IC; and        generating and identification number  ( ID )  for each of the plurality of ICs, wherein the ID for the IC identifies the IC and distinguishes the IC from the other ICs of the plurality of ICs, wherein each of the IDs is a substantial function of random parametric variations in each corresponding IC.      
     
     
       25. The method of  claim 24 , wherein the IDs for each of the plurality of ICs are logged after generation.  
     
     
       26. The method of  claim 25 , wherein the IDs are logged in a database.  
     
     
       27. The method of  claim 24 , wherein the IDs are generated during a test procedure for the ICs.  
     
     
       28. The method of  claim 27 , wherein the IDs are generated via an IC tester.  
     
     
       29. The method of  claim 24 , wherein the plurality of identification cells are formed as separate cells.  
     
     
       30. The method of  claim 24 , wherein the plurality of ICs are manufactured using identical masks, wherein a unique ID is provided for each of the plurality of ICs.  
     
     
       31. The method of  claim 30 , wherein the ID for the IC is used to track the IC and distinguish it from the other of the plurality of ICs.  
     
     
       32. The method of  claim 24 , wherein the plurality of identification cells are formed in the IC as an array.  
     
     
       33. The method of  claim 32 , wherein the array is accessed to generate the ID for the IC based on signals including row and column signals that are applied to the array.  
     
     
       34. The method of  claim 32 , wherein a plurality of dummy identification cells are formed at an edge of the array, wherein the dummy identification cells are not used to generate the ID.  
     
     
       35. The method of  claim 24 , wherein voltages are applied to the plurality of identification cells to disable the identification cells at a time when the identification cells are not being used to generate the ID.  
     
     
       36. The method of  claim 35 , wherein the applied voltages serve to reduce electrical stress on the identification cells when the identification cells are not being used to generate the ID.  
     
     
       37. The method of  claim 24 , wherein the parametric variations are based on mismatches of voltage threshold, transistor length, transistor width, dielectric thickness or other parametric variables in the manufacturing process for the IC.  
     
     
       38. The method of  claim 24 , wherein the plurality of identification cells are provided in a number that is determined based on a total number of ICs to be identified.  
     
     
       39. The method of  claim 38 , wherein the number also is determined based on a drift factor for the manufacturing process used to manufacture the IC.  
     
     
       40. The method of  claim 38 , wherein the number is determined so as to provide an ID of a desired degree of probability.  
     
     
       41. The method of  claim 24 , wherein the IC is employed in a system, wherein the system is operated, wherein the generated ID is used: to track a source of manufacturing; to identify the system employing the IC; to validate a transaction; to route a message; to track an item through customs; to verify a royalty; to recover a stolen good; or to validate software.  
     
     
       42. The method of  claim 24 , wherein the plurality of identification cells are accessed via signals provided internal to the IC.  
     
     
       43. The method of  claim 24 , wherein the plurality of identification cells are accessed via signals provided external to the IC.  
     
     
       44. The method of  claim 24 , wherein the ID is generated by accessing at least certain of the plurality of identification cells in a predetermined sequence.  
     
     
       45. The method of  claim 44 , wherein the predetermined sequence comprises a linear sequence.  
     
     
       46. The method of  claim 44 , wherein the plurality of identification cells are selectively accessed based on a previous measurement of a parametric value associated with particular identification cells.  
     
     
       47. The method of  claim 46 , wherein the plurality of identification cells are selectively accessed to generate a deterministic ID.  
     
     
       48. The method of  claim 24 , wherein the IC also includes one or more cells outputting a predetermined code that is common to a plurality of ICs.  
     
     
       49. The method of  claim 48 , wherein the predetermined code comprises a code that identifies a characteristic of the plurality of ICs or a source of manufacture of the plurality of ICs.  
     
     
       50. The method of  claim 48 , wherein the one or more cells outputting the predetermined code generate the predetermined code based on circuitry that is common with circuitry that generates the ID.  
     
     
       51. The method of  claim 48 , wherein the one or more cells outputting the predetermined code and at least certain of the plurality of identification cells are accessed in a mixed manner to output the predetermined code and to generate the ID.  
     
     
       52. The method of  claim 24 , wherein the ID is generated as a string of bits, wherein one or more bits are indicative of possible errors in the generation of the ID.  
     
     
       53. The method of  claim 24 , wherein the ID is generated based upon a sequence of voltage transitions.  
     
     
       54. The method of  claim 24 , wherein the ID is generated in a unique manner for the particular IC, wherein the manufacturing process for the IC does not require custom process steps or custom circuitry to generate the ID.  
     
     
       55. The method of  claim 24 , wherein the generated ID is stored in a memory.  
     
     
       56. The method of  claim 55 , wherein the memory is accessible by a CPU.  
     
     
       57. The method of  claim 56 , wherein software executed by the CPU makes available the generated ID stored in the memory.  
     
     
       58. The method of  claim 57 , wherein the memory comprises a CPU cache memory.  
     
     
       59. The method of  claim 55 , wherein the memory comprises a non- volatile memory.    
     
     
       60. A method for generating an identification number ( ID ) , the method comprising the steps of:      selectively operating an identification circuit within an integrated circuit  ( IC ) , wherein the identification circuit provides an output that is a substantial function of random parametric variations in the IC, wherein an ID for the IC is generated based on the output, wherein the ID for the IC is a substantial function of random parametric variations in the IC; and        recording the ID, wherein the IC may be identified based on the recorded ID.      
     
     
       61. The method of  claim 60 , wherein an ID for each of a plurality of ICs is generated and logged in a database.  
     
     
       62. The method of  claim 61 , wherein the IDs are generated during a test procedure for the ICs.  
     
     
       63. The method of  claim 62 , wherein the IDs are generated via an IC tester.  
     
     
       64. The method of  claim 60 , wherein the identification circuit comprises a plurality of identification cells.  
     
     
       65. The method of  claim 64 , wherein the plurality of identification cells are formed in the IC as an array.  
     
     
       66. The method of  claim 65 , wherein the array is accessed to generate the ID for the IC based on signals including row and column signals that are applied to the array.  
     
     
       67. The method of  claim 65 , wherein a plurality of dummy identification cells are formed at an edge of the array, wherein the dummy identification cells are not used to generate the ID.  
     
     
       68. The method of  claim 60 , wherein the IC is one of a plurality of ICs that are manufactured using identical masks, wherein a unique ID is provided for each of the plurality of ICs.  
     
     
       69. The method of  claim 68 , wherein the ID for the IC is used to track the IC and distinguish it from the other of the plurality of ICs.  
     
     
       70. The method of  claim 60 , wherein the identification circuit is disabled at a time when the identification circuit is not being used to generate the ID.  
     
     
       71. The method of  claim 70 , wherein voltages applied to the identification circuit serve to reduce electrical stress on the identification circuit when the identification circuit is not being used to generate the ID.  
     
     
       72. The method of  claim 60 , wherein the parametric variations are based on mismatches of voltage threshold, transistor width, dielectric thickness or other parametric variables in a manufacturing process for the IC.  
     
     
       73. The method of  claim 60 , wherein the identification circuit has a number of outputs, wherein the number of outputs of the identification circuit is determined based on a total number of ICs to be identified.  
     
     
       74. The method of  claim 73 , wherein the number of outputs of the identification circuit also is determined based on a drift factor for a manufacturing process used to manufacture the IC.  
     
     
       75. The method of  claim 73 , wherein the number of outputs of the identification circuit is determined so as to provide an ID of a desired degree of probability.  
     
     
       76. The method of  claim 60 , wherein the IC is employed in a system, wherein the system is operated, wherein the generated ID is used: to track a source of manufacturing; to identify the system employing the IC; to validate a transaction; to route a message; to track an item through customs; to verify a royalty; to recover a stolen good; or to validate software.  
     
     
       77. The method of  claim 60 , wherein the identification circuit is accessed via one or more signals provided internal to the IC.  
     
     
       78. The method of  claim 60 , wherein the identification circuit is accessed via one or more signals provided external to the IC.  
     
     
       79. The method of  claim 60 , wherein the ID is generated by accessing at least certain of a plurality of identification cells in a predetermined sequence.  
     
     
       80. The method of  claim 79 , wherein the predetermined sequence comprises a linear sequence.  
     
     
       81. The method of  claim 79 , wherein the plurality of identification cells are selectively accessed based on a previous measurement of a parametric value associated with particular identification cells.  
     
     
       82. The method of  claim 81 , wherein the plurality of identification cells are selectively accessed to generate a deterministic ID.  
     
     
       83. The method of  claim 60 , wherein the IC also includes one or more cells outputting a predetermined code that is common to a plurality of ICs.  
     
     
       84. The method of  claim 83 , wherein the predetermined code comprises a code that identifies a characteristic of the plurality of ICs or a source of manufacture of the plurality of ICs.  
     
     
       85. The method of  claim 83 , wherein the one or more cells outputting the predetermined code generate the predetermined code based on circuitry that is at least in part common with the identification circuit.  
     
     
       86. The method of  claim 83 , wherein the one or more cells outputting the predetermined code and at least a part of the output of the identification circuit are output in a mixed manner to output the predetermined code and to generate the ID.  
     
     
       87. The method of  claim 60 , wherein the ID is generated as a string of bits, wherein one of more bits are indicative of possible errors in the generation of the ID.  
     
     
       88. The method of  claim 60 , wherein the ID is generated based upon a sequence of voltage transitions.  
     
     
       89. The method of  claim 60 , wherein the ID is generated in a unique manner for the IC, wherein a manufacturing process for the IC does not require custom process steps or custom circuitry to generate the ID.  
     
     
       90. The method of  claim 60 , wherein the generated ID is stored in a memory.  
     
     
       91. The method of  claim 90 , wherein the memory is accessible by a CPU.  
     
     
       92. The method of  claim 91 , wherein software executed by the CPU makes available the generated ID stored in the memory.  
     
     
       93. The method of  claim 92 , wherein the memory comprises a CPU cache memory.  
     
     
       94. The method of  claim 90 , wherein the memory comprises a non- volatile memory.    
     
     
       95. A method for identifying a system using an identification number ( ID ) , the method comprising the steps of:      operating the system, wherein the system employs an integrated circuit  ( IC ) , wherein the IC includes a plurality of identification cells each having an output that is a substantial function of random parametric variations in the IC;        generating the ID in response to the outputs of the plurality of identification cells, wherein the ID is a substantial function of random parametric variations in the IC.      
     
     
       96. The method of  claim 95 , wherein an ID for each of a plurality of ICs is generated and logged in a database.  
     
     
       97. The method of  claim 96 , wherein the IDs are generated during a test procedure for the ICs.  
     
     
       98. The method of  claim 97 , wherein the IDs are generated via an IC tester.  
     
     
       99. The method of  claim 95 , wherein the plurality of identification cells are formed as separate cells.  
     
     
       100. The method of  claim 95 , wherein a plurality of ICs are manufactured using identical masks, wherein a unique ID is provided for each of the plurality of ICs.  
     
     
       101. The method of  claim 100 , wherein the ID for the IC is used to track the IC and distinguish it from the other of the plurality of ICs.  
     
     
       102. The method of  claim 95 , wherein the plurality of identification cells are formed in the IC as an array.  
     
     
       103. The method of  claim 102 , wherein the array is accessed to generate the ID for the IC based on signals including row and column signals that are applied to the array.  
     
     
       104. The method of  claim 102 , wherein a plurality of dummy identification cells are formed at an edge of the array, wherein the dummy identification cells are not used to generate the ID.  
     
     
       105. The method of  claim 95 , wherein voltages are applied to the plurality of identification cells to disable the identification cells at a time when the identification cells are not being used to generate the ID.  
     
     
       106. The method of  claim 105 , wherein the applied voltages serve to reduce electrical stress on the identification cells when the identification cells are not being used to generate the ID.  
     
     
       107. The method of  claim 95 , wherein the parametric variations are based on mismatches of voltage threshold, transistor length, transistor width, dielectric thickness or other parametric variables in a manufacturing process for the IC.  
     
     
       108. The method of  claim 95 , wherein the plurality of identification cells are provided in a number that is determined based on a total number of ICs to be identified.  
     
     
       109. The method of  claim 108 , wherein the number also is determined based on a drift factor for a manufacturing process used to manufacture the IC.  
     
     
       110. The method of  claim 108 , wherein the number is determined so as to provide an ID of a desired degree of probability.  
     
     
       111. The method of  claim 95 , wherein the IC is employed in a system, wherein the system is operated, wherein the generated ID is used: to track a source of manufacturing; to identify the system employing the IC; to validate a transaction; to route a message; to track an item through customs; to verify a royalty; to recover a stolen good; or to validate software.  
     
     
       112. The method of  claim 95 , wherein the plurality of identification cells are accessed via signals provided internal to the IC.  
     
     
       113. The method of  claim 95 , wherein the plurality of identification cells are accessed via signals provided external to the IC.  
     
     
       114. The method of  claim 95 , wherein the ID is generated by accessing at least certain of the plurality of identification cells in a predetermined sequence.  
     
     
       115. The method of  claim 114 , wherein the predetermined sequence comprises a linear sequence.  
     
     
       116. The method of  claim 114 , wherein the plurality of identification cells are selectively accessed based on a previous measurement of a parametric value associated with particular identification cells.  
     
     
       117. The method of  claim 116 , wherein the plurality of identification cells are selectively accessed to generate a deterministic ID.  
     
     
       118. The method of  claim 95 , wherein the IC also includes one or more cells outputting a predetermined code that is common to a plurality of ICs.  
     
     
       119. The method of  claim 118 , wherein the predetermined code comprises a code that identifies a characteristic of the plurality of ICs or a source of manufacture of the plurality of ICs.  
     
     
       120. The method of  claim 118 , wherein the one or more cells outputting the predetermined code generate the predetermined code based on circuitry that is common with circuitry that generates the ID.  
     
     
       121. The method of  claim 118 , wherein the one or more cells outputting the predetermined code and at least certain of the plurality of identification cells are accessed in a mixed manner to output the predetermined code and to generate the ID.  
     
     
       122. The method of  claim 95 , wherein the ID is generated as a string of bits, wherein one or more bits are indicative of possible errors in the generation of the ID.  
     
     
       123. The method of  claim 95 , wherein the ID is generated based upon a sequence of voltage transitions.  
     
     
       124. The method of  claim 95 , wherein the ID is generated in a unique manner for the particular IC, wherein a manufacturing process for the IC does not require custom process steps or custom circuitry to generate the ID.  
     
     
       125. The method of  claim 95 , wherein the generated ID is stored in a memory.  
     
     
       126. The method of  claim 125 , wherein the memory comprises a non- volatile memory.    
     
     
       127. The method of  claim 125 , wherein the memory is accessible by a CPU.  
     
     
       128. The method of  claim 127 , wherein software executed by the CPU makes available the generated ID stored in the memory.  
     
     
       129. The method of  claim 125 , wherein the memory comprises a CPU cache memory.  
     
     
       130. A method for identifying a system based on an identification number ( ID ) , the method comprising the steps of:      generating the ID with an identification circuit within an integrated circuit  ( IC )  employed in the system, wherein the identification circuit provides an output that is a substantial function of random parametric variations in the IC, wherein the ID is generated based on the output, wherein the ID is a substantial function of random parametric variations in the IC; and        identifying the system based on the ID.      
     
     
       131. The method of  claim 130 , wherein the IDs for each of a plurality of ICs are logged in a database.  
     
     
       132. The method of  claim 131 , wherein the IDs are generated during a test procedure for the ICs.  
     
     
       133. The method of  claim 130 , wherein the IDs are generated via an IC tester.  
     
     
       134. The method of  claim 130 , wherein the identification circuit comprises a plurality of identification cells.  
     
     
       135. The method of  claim 134 , wherein the plurality of identification cells are formed in the IC as an array.  
     
     
       136. The method of  claim 135 , wherein the array is accessed to generate the ID for the IC based on signals including row and column signals that are applied to the array.  
     
     
       137. The method of  claim 135 , wherein a plurality of dummy identification cells are formed at an edge of the array, wherein the dummy identification cells are not used to generate the ID.  
     
     
       138. The method of  claim 134 , wherein voltages are applied to the plurality of identification cells to disable the identification cells at a time when the identification cells are not being used to generate the ID.  
     
     
       139. The method of  claim 138 , wherein the applied voltages serve to reduce electrical stress on the identification cells when the identification cells are not being used to generate the ID.  
     
     
       140. The method of  claim 134 , wherein the plurality of identification cells are provided in a number that is determined based on a total number of ICs to be identified.  
     
     
       141. The method of  claim 140 , wherein the number also is determined based on a drift factor for a manufacturing process used to manufacture the IC.  
     
     
       142. The method of  claim 140 , wherein the number is determined so as to provide an ID of a desired degree of probability.  
     
     
       143. The method of  claim 134 , wherein the plurality of identification cells are accessed via signals provided internal to the IC.  
     
     
       144. The method of  claim 134 , wherein the plurality of identification cells are accessed via signals provided external to the IC.  
     
     
       145. The method of  claim 134 , wherein the ID is generated by accessing at least certain of the plurality of identification cells in a predetermined sequence.  
     
     
       146. The method of  claim 145 , wherein the predetermined sequence comprises a linear sequence.  
     
     
       147. The method of  claim 145 , wherein the plurality of identification cells are selectively accessed based on a previous measurement of a parametric value associated with particular identification cells.  
     
     
       148. The method of  claim 147 , wherein the plurality of identification cells are selectively accessed to generate a deterministic ID.  
     
     
       149. The method of  claim 134 , wherein the IC also includes one or more cells outputting a predetermined code that is common to a plurality of ICs.  
     
     
       150. The method of  claim 149 , wherein the predetermined code comprises a code that identifies a characteristic of the plurality of ICs or a source of manufacture of the plurality of ICs.  
     
     
       151. The method of  claim 149 , wherein the one or more cells outputting the predetermined code generate the predetermined code based on circuitry that is at least in part common with circuitry that generates the ID.  
     
     
       152. The method of  claim 149 , wherein the one or more cells outputting the predetermined code and at least certain of the plurality of identification cells are accessed in a mixed manner to output the predetermined code and to generate the ID.  
     
     
       153. The method of  claim 130 , wherein a plurality of ICs are manufactured using identical masks, wherein a unique ID is provided for each of the plurality of ICs.  
     
     
       154. The method of  claim 153 , wherein the ID for the IC is used to track the IC and distinguish it from other of the plurality of ICs.  
     
     
       155. The method of  claim 130 , wherein the parametric variations are based on mismatches of voltage threshold, transistor length, transistor width, dielectric thickness or other parametric variables in a manufacturing process for the IC.  
     
     
       156. The method of  claim 130 , wherein the IC is employed in a system, wherein the system is operated, wherein the generated ID is used: to track a source of manufacturing; to identify the system employing the IC; to validate a transaction; to route a message; to track an item through customs; to verify a royalty; to recover a stolen good; or to validate software.  
     
     
       157. The method of  claim 130 , wherein the ID is generated as a string of bits, wherein one or more bits are indicative of possible errors in the generation of the ID.  
     
     
       158. The method of  claim 130 , wherein the ID is generated based upon a sequence of voltage transitions.  
     
     
       159. The method of  claim 130 , wherein the ID is generated in a unique manner for a particular IC, wherein a manufacturing process for the IC does not require custom process steps or custom circuitry to generate the ID.  
     
     
       160. The method of  claim 130 , wherein the generated ID is stored in a memory.  
     
     
       161. The method of  claim 160 , wherein the memory is accessible by a CPU.  
     
     
       162. The method of  claim 161 , wherein software executed by the CPU makes available the generated ID stored in the memory.  
     
     
       163. The method of  claim 162 , wherein the memory comprises a CPU cache memory.  
     
     
       164. The method of  claim 160 , wherein the memory comprises a non- volatile memory.