Infrared imaging system employing on-focal plane nonuniformity correction

Abstract

An infrared imaging system having a focal plane array including an array of detector elements and a readout circuit and including nonuniformity correction circuitry on the focal plane array. The individual detector elements correspond to pixels of an infrared scene to be imaged. Offsets in detection signals from each pixel arising from nonuniformities in the individual detector elements in the array are corrected by storing offset correction values for each detector element and using the stored offset values to control correction circuitry as the respective detector element signals are read out. The detector array and readout circuit are preferably formed as a monolithic or hybrid structure and the offset correction is provided on the focal plane array prior to signal amplification and analog to digital conversion.

1. An infrared imaging system, comprising:
 an infrared focal plane array comprising: 
 a plurality of infrared detector elements arranged in an array;  
 a readout circuit electrically coupled to the plurality of detector elements and comprising means for biasing the plurality of detector elements so as to provide separate detection signals corresponding to each detector element in the array, in response to incident infrared radiation and means for separately correcting offsets in the detection signals Provided  provided from the plurality of elements in the detector array to compensate for nonuniformities in the detector elements, wherein said means for correcting comprises: 
 a correction circuit including a plurality of parallel connected circuit elements; and  
 means for selectively electrically connecting said circuit elements into the detector readout circuit in response to stored offset correction values; and  
 
 output means for providing the corrected detection signals as an output of the focal plane array;  
 
 means for storing a plurality of offset correction values corresponding to the plurality of detector elements; and  
 means for providing the offset correction values to said means for correcting.  
 
     
     
       2. An infrared imaging system as set out in  claim 1 , wherein said plurality of parallel connected circuit elements comprise a plurality of capacitors. 
     
     
       3. An infrared imaging system as set out in  claim 2 , wherein said capacitors have capacitances of 2 N C 0 , respectively, where C 0  is a fixed capacitance and N is a nonnegative integer. 
     
     
       4. An infrared imaging system as set out in  claim 3 , wherein there are four capacitors having respective capacitances of C 0 , 2C 0 , 4C 0  and 8C 0 . 
     
     
       5. An infrared imaging system as set out in  claim 1 , wherein said means for selectively connecting comprises a plurality of switches, equal in number to said plurality of parallel connected circuit elements and connected in series therewith. 
     
     
       6. An infrared imaging system as set out in  claim 1 , wherein said offset correction values are binary values and wherein said means for storing comprises a digital memory. 
     
     
       7. An infrared imaging system as set out in  claim 6 , wherein said digital memory stores a separate binary offset correction value for each detector element in the array. 
     
     
       8. An infrared imaging system as set out in  claim 1 , wherein said plurality of detector elements are arranged in a plurality of rows and columns and wherein said means for correcting comprises a separate offset correction circuit for each column and wherein said means for providing said offset correction values provides said offset correction values in a time multiplexed manner to said means for correcting. 
     
     
       9. An infrared imaging system as set out in  claim 1 , wherein said plurality of parallel connected circuit elements comprise a plurality of constant current sources. 
     
     
       10. An infrared imaging system as set out in  claim 9 , wherein said current sources provide substantially constant currents of 2 N I 0 , respectively, when coupled into said readout circuit by said means for selectively connecting, where I 0  is a fixed current value and N is a nonnegative integer. 
     
     
       11. An infrared imaging system as set out in  claim 10 , wherein there are four constant current sources providing substantially constant currents of I 0 , 2I 0 , 4I 0  and 8I 0 . 
     
     
       12. An infrared imaging system as set out in  claim 1 , wherein said array of detector elements and said readout circuit are formed as a single monolithic integrated circuit chip. 
     
     
       13. An infrared imaging system as set out in  claim 1 , wherein said plurality of detector elements comprise microbolometer detector elements. 
     
     
       14. An infrared imaging system as set out in  claim 13 , wherein said means for biasing comprises a constant current source coupled to said microbolometer detector elements. 
     
     
       15. An infrared imaging system as set out in  claim 13 , wherein said means for biasing comprises a fixed voltage source coupled to said microbolometer detector elements. 
     
     
       16. An infrared imaging system as set out in  claim 15 , wherein said means for correcting comprises a plurality of substantially constant current sources selectively coupled to said voltage source and in parallel with said microbolometer detector elements. 
     
     
       17. An infrared imaging system as set out in  claim 16 , wherein said means for correcting further comprises a plurality of switches coupled in series with respective constant current sources. 
     
     
       18. An infrared imaging system as set out in  claim 17 , wherein said offset correction values comprise an on or off signal supplied to each of said switches. 
     
     
       19. An infrared imaging system as set out in  claim 1 , wherein said output means comprises one or more output buffers. 
     
     
       20. An infrared imaging system as set out in  claim 1 , wherein said focal plane array further comprises a differential amplifier with first and second inputs wherein the first input is electrically connected to the readout circuit so as to receive the detection signals and wherein the second input is connected to an adjustable reference voltage. 
     
     
       21. An infrared imaging system as set out in  claim 1 , further comprising timing means for providing focal plane timing signals to said readout circuit. 
     
     
       22. An infrared imaging system as set out in  claim 21 , wherein said readout circuit further comprises offset correction logic means for controlling the means for correcting in response to said timing signals provided from the timing means. 
     
     
       23. An infrared imaging system as set out in  claim 22 , wherein said offset correction logic means receives said offset correction values from said means for storing and provide them to said means for correcting in response to said timing signals. 
     
     
       24. An infrared imaging system as set out in  claim 1 , further comprising means, coupled to said output means, for analog to digital converting the corrected detection signals and providing corresponding image data for each detector element. 
     
     
       25. An infrared imaging system as set out in  claim 24 , further comprising a memory for temporarily storing image data corresponding to all the detector elements of the array. 
     
     
       26. An infrared imaging system, comprising:
 an infrared focal plane array comprising: 
 a plurality of infrared detector elements arranged in an array;  
 a readout circuit electrically coupled to the plurality of detector elements and comprising a plurality of readout cells equal in number to the plurality of detector elements, means for biasing the plurality of detector elements so as to provide separate detection signals corresponding to each detector element in the array, in response to incident infrared radiation and means for separately correcting offsets in the detection signals provided from the plurality of elements in the detector array to compensate for nonuniformities in the detector elements, wherein said means for correcting comprises an offset correction and circuit in each readout cell of the readout circuit and wherein each offset correction circuit comprises a plurality of parallel connected circuit elements and means for selectively electrically connecting said circuit elements into the readout cell in response to a stored offset correction value corresponding to said readout cell; and  
 output means for providing the corrected detection signals as an output of the focal plane array;  
 
 means for storing a plurality of offset correction values corresponding to the plurality of detector elements; and  
 means for providing the offset correction values to said means for correcting.  
 
     
     
       27. An infrared focal plane array, comprising:
 a plurality of detector elements configured in a two dimensional array; and  
 a readout circuit electrically coupled to said plurality of detector elements and structurally integrated therewith, said readout circuit comprising: 
 a sample and hold capacitor;  
 means for biasing the detector elements so as to provide an analog detection signal from each detector element corresponding to the infrared radiation incident thereon, wherein the analog detection signal is a voltage signal provided at a sample node coupled to the sample and hold capacitor; and  
 means for correcting the analog detection signal from each detector element by a discrete offset correction and providing a corrected analog detection signal, wherein the discrete offset correction varies from detector element to detector element and comprises an offset correction voltage added to, or subtracted from, the analog detection signal, wherein said means for correcting subtracts or adds a variable amount of charge from said sample and hold capacitor to provide a corrected voltage signal at said sample node, and wherein said means for correcting comprises a plurality of capacitors connected between said sample node and a reference voltage and a corresponding plurality of switches coupled in series with each respective capacitor and said reference voltage, wherein said plurality of switches are selectively turned on or off to provide a desired amount of discrete offset correction for each detector element.  
 
 
     
     
       28. An infrared focal plane array as set out in  claim 27 , wherein said readout circuit further comprises means for controlling said means for correcting so as to selectively open and close said plurality of switches in a time multiplexed manner during readout of a plurality of separate detector elements. 
     
     
       29. An infrared focal plane array as set out in  claim 27 , wherein said detector elements comprise microbolometer detector elements. 
     
     
       30. An infrared focal plane array as set out in  claim 29 , wherein said means for said biasing comprises a constant current source coupled to said microbolometer detector elements and said sample and hold capacitor. 
     
     
       31. An infrared focal plane array as set out in  claim 27 , wherein said readout circuit further comprises a differential amplifier having first and second inputs, the first input thereof coupled to said sample node and said second input thereof coupled to a adjustable voltage source. 
     
     
       32. An infrared focal plane array as set out in  claim 31 , wherein said readout circuit further comprises a feedback capacitor coupled between the output of the differential amplifier and said first input thereof. 
     
     
       33. An infrared focal plane array as set out in  claim 32 , wherein said readout circuit further comprises a switch coupled between and parallel with said feedback capacitor between the output of the differential amplifier and the first input thereof. 
     
     
       34. An infrared focal plane array as set out in  claim 27  wherein said plurality of detector elements and said readout circuit are formed as a single monolithic integrated circuit wherein said readout circuit acts as a substrate for said detector elements. 
     
     
       35. An infrared focal plane array, comprising:
 a plurality of detector elements configured in a two dimensional array; and  
 a readout circuit electrically coupled to said plurality of detector elements and structurally integrated therewith, said readout circuit comprising: 
 a sample and hold capacitor;  
 means for biasing the detector elements so as to provide an analog detection signal from each detector element corresponding to the infrared radiation incident thereon, wherein the analog detection signal is a voltage signal provided at a sample node coupled to the sample and hold capacitor; and  
 means for correcting the analog detection signal from each detector element by a discrete offset correction and providing a corrected analog detection signal, wherein the discrete offset correction varies from detector element to detector element and comprises an offset correction voltage added to, or subtracted from, the voltage signal, wherein said means for correcting subtracts or adds a variable amount of charge from said sample and hold capacitor to provide a corrected voltage signal at said sample node, and wherein said means for correcting comprises a plurality of parallel connected constant current sources connected between said sample node and a reference voltage and a plurality of switches corresponding to said plurality of constant current sources and respectively coupled in series therewith.  
 
 
     
     
       36. An infrared imaging system, comprising:
   an infrared focal plane array comprising:      a plurality of infrared detector elements arranged in an array;        a readout circuit electrically coupled to the plurality of detector elements and comprising means for biasing the plurality of detector elements so as to provide separate detection signals corresponding to each detector element in the array, in response to incident infrared radiation and means for separately correcting offsets in the detection signals provided from the plurality of elements in the detector array to compensate for nonuniformities in the detector elements, wherein said means for correcting comprises:      a correction circuit including a plurality of circuit elements; and        means for selectively electrically connecting said circuit elements into the detector readout circuit in response to stored offset correction values; and          output means for providing the corrected detection signals as an output of the focal plane array;          means for storing a plurality of offset correction values corresponding to the plurality of detector elements; and        means for providing the offset correction values to said means for correcting.     
     
     
       37. An infrared imaging system as set out in  claim 36 , wherein said plurality of circuit elements comprise a plurality of capacitors. 
     
     
       38. An infrared imaging system as set out in  claim 36 , wherein said means for selectively connecting comprises a plurality of switches, equal in number to said plurality of circuit elements and connected in series therewith. 
     
     
       39. An infrared imaging system as set out in  claim 36 , wherein said plurality of circuit elements comprise a plurality of constant current sources. 
     
     
       40. An infrared imaging system as set out in  claim 36 , further comprising means, coupled to said output means, for analog to digital converting the corrected detection signals and providing corresponding image data for each detector element. 
     
     
       41. An infrared imaging system as set out in  claim 36 , wherein said plurality of detector elements comprise microbolometer detector elements. 
     
     
       42. An infrared imaging system as set out in  claim 36 , wherein said offset correction values are binary values and wherein said means for storing comprises a digital memory. 
     
     
       43. An infrared imaging system as set out in  claim 36 , wherein said array of detector elements and said readout circuit are formed as a single monolithic integrated circuit chip. 
     
     
       44. An infrared imaging system as set out in  claim 36 , further comprising timing means for providing focal plane timing signals to said readout circuit. 
     
     
       45. An infrared imaging system as set out in  claim 36 , wherein said plurality of detector elements are arranged in a plurality of rows and columns and wherein said means for correcting comprises a separate offset correction circuit for each column and wherein said means for providing said offset correction value provides said offset correction values in a time multiplexed manner to said means for correcting. 
     
     
       46. An infrared imaging system as set out in  claim 36 , wherein said output means comprises one or more output buffers. 
     
     
       47. An infrared imaging system as set out in  claim 36 , wherein said focal plane array further comprises a differential amplifier with first and second inputs wherein the first input is electrically connected to the readout circuit so as to receive the detection signals and wherein the second input is connected to an adjustable reference voltage. 
     
     
       48. An infrared imaging system, comprising:
   an infrared focal plane array comprising:      a plurality of infrared detector elements arranged in an array;        a readout circuit electrically coupled to the plurality of detector elements and comprising a plurality of readout cells equal in number to the plurality of detector elements, means for biasing the plurality of detector elements so as to provide separate detection signals corresponding to each detector element in the array, in response to incident infrared radiation and means for separately correcting offsets in the detection signals provided from the plurality of elements in the detector array to compensate for nonuniformities in the detector elements, wherein said means for correcting comprises an offset correction circuit in each readout cell of the readout circuit and wherein each offset correction circuit comprises a plurality of circuit elements and means for selectively electrically connecting said circuit elements into the readout cell in response to a stored offset correction value corresponding to said readout cell; and          output means for providing the corrected detection signals as an output of the focal plane array;        means for storing a plurality of offset correction values corresponding to the plurality of detector elements; and        means for providing the offset correction values to said means for correcting.     
     
     
       49. An infrared focal plane array, comprising:
   a plurality of detector elements configured in a two dimensional array; and        a readout circuit electrically coupled to said plurality of detector elements and structurally integrated therewith, said readout circuit comprising:      a sample and hold capacitor;        means for biasing the detector elements so as to provide an analog detection signal from each detector element corresponding to the infrared radiation incident thereon, wherein the analog detection signal is a voltage signal provided at a sample node coupled to the sample and hold capacitor; and        means for correcting the analog detection signal from each detector element by a discrete offset correction and providing a corrected analog detection signal, wherein the discrete offset correction varies from detector element to detector element and comprises an offset correction voltage added to, or subtracted from, the analog detection signal, wherein said means for correcting subtracts or adds a variable amount of charge from said sample and hold capacitor to provide a corrected voltage signal at said sample node, and wherein said means for correcting comprises a plurality of circuit elements connected between said sample node and a reference voltage and a corresponding plurality of switches coupled in series with each respective circuit element and said reference voltage, wherein said plurality of switches selectively provide a desired amount of discrete offset correction for each detector element.       
     
     
       50. An infrared focal plane array as set out in  claim 49 , wherein said readout circuit further comprises means for controlling said means for correcting so as to selectively open and close said plurality of switches in a time multiplexed manner during readout of a plurality of separate detector elements. 
     
     
       51. An infrared focal plane array as set out in  claim 49 , wherein said detector elements comprise microbolometer detector elements. 
     
     
       52. An infrared focal plane array as set out in  claim 49 , wherein said readout circuit further comprises a differential amplifier having first and second inputs, the first input thereof coupled to said sample node and said second input thereof coupled to a adjustable voltage source. 
     
     
       53. An infrared focal plane array as set out in  claim 49  wherein said plurality of detector elements and said readout circuit are formed as a single monolithic integrated circuit wherein said readout circuit acts as a substrate for said detector elements. 
     
     
       54. An infrared focal plane array, comprising:
   a plurality of detector elements configured in a two dimensional array; and        a readout circuit electrically coupled to said plurality of detector elements and structurally integrated therewith, said readout circuit comprising:      a sample and hold capacitor;        means for biasing the detector elements so as to provide an analog detection signal from each detector element corresponding to the infrared radiation incident thereon, wherein the analog detection signal is a voltage signal provided at a sample node coupled to the sample and hold capacitor; and        means for correcting the analog detection signal from each detector element by a discrete offset correction and providing a corrected analog detection signal, wherein the discrete offset correction varies from detector element to detector element and comprises an offset correction voltage added to, or subtracted from, the voltage signal, wherein said means for correcting subtracts or adds a variable amount of charge from said sample and hold capacitor to provide a corrected voltage signal at said sample node, and wherein said means for correcting comprises a plurality of constant current sources connected between said sample node and a reference voltage and a plurality of switches corresponding to said plurality of constant current sources and respectively coupled in series therewith.