Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase operational speed

Abstract

A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.

1. A semiconductor memory comprising:
 a plurality of first regions in lattice fashion, each of which corresponds to a memory array including a plurality of main word lines extending in a first direction, a plurality of sets of sub-word lines extending in said first direction, a plurality of pairs of data lines extending in a second direction perpendicular to said first direction and a plurality of memory cells, each of which is coupled to a corresponding one of said plurality of sub-word lines and a corresponding one of said data lines, one of said plurality of main word lines being allotted to one of said plurality of sets of sub-word lines;    a plurality of second regions, each of which is arranged alternately with each of said first regions arranged along said first direction and each of which includes sub-word line drivers connected to said sub-word lines;    a plurality of third regions, each of which is arranged alternately with each of said first regions arranged along said second direction and each of which includes sense amplifiers connected to said data lines; and    a plurality of fourth regions, each of which is arranged alternately with each of said third regions arranged along said first direction;    wherein each of said plurality of main word lines extends through one or more of said first regions arranged along said first direction;    wherein said semiconductor memory further includes:    a plurality of pairs of sub-common data lines, each of which extends through said third regions arranged along said first direction;    first switching circuits formed in said third regions and connected interposingly between said plurality of pairs of data lines and a corresponding one of said pairs of sub-common data lines;    a plurality of pairs of main-common data lines, each of which extends through one or more of second regions arranged along said second direction; and    second switching circuits formed in said fourth regions and connected interposingly between a corresponding one of said pairs of main-common data lines and a corresponding one of said pairs of sub-common data lines.    
     
     
       2. A semiconductor memory according to  claim 1 ,
 wherein a number of memory arrays allotted to one of said main word-lines is greater than a number of memory arrays alloted to a corresponding one of said pairs of sub-common data lines.    
     
     
       3. A semiconductor memory according to  claim 1 ,
 wherein a length of said each main word-line is longer than a length of said each pair of sub-common data lines.    
     
     
       4. A semiconductor memory comprising:
 a first region extending in a first direction;    a second region extending in said first direction and in parallel with said first region;    a third region extending in a second direction perpendicular to said first direction;    a fourth region formed as a rectangle, two sides of which are contiguous to said first region and said third region, respectively; and    a fifth region formed as a rectangle, three sides of which are contiguous to said first region, said second region and said third region, respectively;    wherein said third region includes a pair of main common data lines extending in said second direction,    wherein said fourth region includes a first memory array having a plurality of first main word lines extending in said first direction, a plurality of sets of first sub-word lines extending in said first direction, a plurality of pairs of first data lines extending in said second direction and a plurality of first dynamic memory cells, each of which is coupled to a corresponding one of said plurality of first sub-word lines, each of said sets of first sub-word lines corresponding to one of said plurality of first main word lines,    wherein said fifth region includes a second memory array having a plurality of second main word lines extending in said first direction, a plurality of sets of second sub-word lines extending in said first direction, a plurality of pairs of second data lines extending in said second direction and a plurality of second dynamic memory cells, each of which is coupled to a corresponding one of said plurality of second sub-word lines, each of said sets of second sub-word lines corresponding to one of said plurality of second main word lines,    wherein said first region includes: 
 (1) a pair of first sub-common data lines extending in said first direction,  
 (2) first sense amplifiers connected to said plurality of pairs of first data lines and  
 (3) first switching circuits connected interposingly between said plurality of pairs of first data lines and said pair of first sub-common data lines,  
   wherein said second region includes: 
 (1) a pair of second sub-common data lines extending in said first direction,  
 (2) second sense amplifiers connected to said plurality of pairs of second data lines and  
 (3) second switching circuits connected interposingly between said plurality of pairs of second data lines and said pair of second sub-common data lines,  
   wherein said first region and said third region intersect in a first crossing area including: 
 (1) a third switching circuit connected interposingly between said pair of main common data lines,  
 (2) a fourth switching circuit which provides said first sense amplifiers with a first positive power supply voltage, and  
 (3) a fifth switching circuit which provides said first sense amplifiers with a second positive power supply voltage lower than said first positive power supply voltage, and  
   wherein said second region and said third region intersect in a second crossing area including: 
 (1) a sixth switching circuit connected interposingly between said pair of main common data lines,  
 (2) a seventh switching circuit which provides said second sense amplifiers with said first positive power supply voltage, and  
 (3) an eighth switching circuit which provides said second sense amplifiers with said second positive power supply voltage.  
   
     
     
       5. A semiconductor memory according to  claim 4 ,
 wherein said third region includes first sub-word line drivers coupled to said first sub-word lines and second sub-word line drivers coupled to said second sub-word lines.    
     
     
       6. A semiconductor memory according to  claim 4 ,
 wherein each of said first and second sense amplifiers includes a pair of PMOS transistors and a pair of NMOS transistors, each of said pairs of PMOS and NMOS transistors having sources coupled in common, drains coupled to corresponding pairs of data lines and dates cross-coupled to said drains,    wherein each of said first and second sense amplifiers provides said corresponding pair of data lines with a pair of complementary signals having a high side voltage and a low side voltage on the basis of information of a corresponding one of said dynamic memory cells,    wherein, in a first period, said first and second sense amplifiers are driven by said first positive power supply voltage, and    wherein, in a second period following said first period, said first and second sense amplifiers are driven by said second positive power supply voltage.    
     
     
       7. A semiconductor memory comprising:
 a first region extending in a first direction;    a second region extending in said first direction and in parallel with said first region;    a third region extending in a second direction perpendicular to said first direction;    a fourth region formed as a rectangle, two sides of which are contiguous to said first region and said third region, respectively; and    a fifth region formed as a rectangle, three sides of which are contiguous to said first region, said second region and said third region, respectively;    wherein said third region includes a pair of main common data lines extending in said second direction,    wherein said fourth region includes a first memory array having a plurality of first main word lines extending in said first direction, a plurality of sets of first sub-word lines extending in said first direction, a plurality of pairs of first data lines extending in said second direction and a plurality of first dynamic memory cells, each of which is coupled to a corresponding one of said plurality of first sub-word lines, each of said sets of first sub-word lines corresponding to one of said plurality of first main word lines,    wherein said fifth region includes a second memory array having a plurality of second main word lines extending in said first direction, a plurality of sets of second sub-word lines extending in said first direction, a plurality of pairs of second data lines extending in said second direction and a plurality of second dynamic memory cells, each of which is coupled to a corresponding one of said plurality of second sub-word lines, each of said sets of second sub-word lines corresponding to one of said plurality of second main word lines,    wherein said first region includes: 
 (1) a pair of first sub-common data lines extending in said first direction,  
 (2) first sense amplifiers connected to said plurality of pairs of first data lines and  
 (3) first switching circuits connected interposingly between said plurality of pairs of first data lines and said pair of first sub-common data lines,  
   wherein said second region includes: 
 (1) a pair of second sub-common data lines extending in said first direction,  
 (2) second sense amplifiers connected to said plurality of pairs of second data lines, and  
 (3) second switching circuits connected interposingly between said plurality of pairs of second data lines and said pair of second sub-common data lines,  
   wherein said first region and said third region intersect in a first crossing area including a third switching circuit connected interposingly between said pair of first sub-common data lines and said pair of main common data lines,    wherein said second region and said third region intersect in a second crossing area including a fourth switching circuit connecting interposingly between said pair of second sub-common data lines and said pair of main common data lines, and    wherein each of said first and second sub-word line drivers include: 
 (1) a first PMOS transistor having a gate connected to a corresponding one of said main word lines, a drain connected to a corresponding one of said sub-word lines and a source receiving a first signal,  
 (2) a first NMOS transistor having a gate connected to the gate of said first PMOS transistor, a drain connected to the drain of said first PMOS transistor and a source connected to a ground potential, and  
 (3) a second NMOS transistor having a drain connected to the drain of said first NMOS transistor, a source connected to said ground potential and a gate receiving a second signal, said first and second signals being complementary signals.  
   
     
     
       8. A semiconductor memory according to  claim 7 , wherein said semiconductor memory is formed on a P-type substrate comprising:
 (1) a first N-well,    (2) a second N-well formed in said first N-well,    (3) a first P-well formed in said first N-well, and    (4) a second P-well formed in said first N-well,    wherein the source and the drain of said first PMOS are in said second N-well,    wherein the source and the drain of said first NMOS are in said first P-well, and    wherein the source and the drain of a switching NMOS transistor, forming one of said dynamic memory cells, are in said second P-well.    
     
     
       9. A semiconductor memory according to  claim 8 , wherein said first N-well is supplied with a voltage corresponding to a high level of said first signal, and
 wherein said P-type substrate is supplied with said ground potential.    
     
     
       10. A semiconductor memory comprising:
   a first main word line extending in a first direction;        a first memory array including a plurality of first sub word lines coupled to the first main word line and extending in the first direction, a plurality of first bit lines extending in a second direction which intersects with the first direction, and a plurality of first memory cells provided at intersections of the plurality of first sub word line and the plurality of first bit lines;        a second main word line extending in the first direction;        a second memory array including a plurality of second sub word lines coupled to the second main word line and extending in the first direction, a plurality of second bit lines extending in the second direction, and a plurality of second memory cells provided at intersections of the plurality of second sub word lines and the plurality of second bit lines;        a first sub common IO line pair extending in the first direction and coupled to the plurality of first bit lines via a plurality of first switch circuits;        a second sub common IO line pair extending in the first direction and coupled to the plurality of second bit lines via a plurality of second switch circuits;        a first main common IO line pair extending in the second direction;        a first sub amplifier coupled between the first sub common IO line pair and the first main common IO line pair; and        a second sub amplifier coupled between the second sub common IO line pair and the first main common IO line pair,        wherein the first sub amplifier includes a first MOSFET having a gate which is coupled to one line of the first sub common IO line pair, a second MOSFET having a gate which is coupled to the other line of the first sub common IO line pair and having a source which is coupled to a source of the first MOSFET at a first node, a third MOSFET coupled between the first node and a first potential, a fourth MOSFET coupled between a drain of the first MOSFET and one line of the first main common IO line pair, and a fifth MOSFET coupled between a drain of the second MOSFET and the other line of the first main common IO line, and        wherein the second sub amplifier includes a sixth MOSFET having a gate which is coupled to one line of the second sub common IO line pair, a seventh MOSFET having a gate which is coupled to the other line of the second sub common IO line pair and having a source which is coupled to a source of the sixth MOSFET at a second node, a eighth MOSFET coupled between the second node and the first potential, a ninth MOSFET coupled between a drain of the sixth MOSFET and one line of the first main common IO line pair, a tenth MOSFET coupled between a drain of seventh MOSFET and the other line of the first main common IO line pair,        further comprising:        a plurality of bit line selection signal lines coupled to the plurality of the first and second switch circuits,        wherein the plurality of bit line selection signal lines and the first main common IO line are formed on the same layer, and        wherein the first and second main word lines and the first and second sub common IO lines are formed on the same layer.     
     
     
       11. A semiconductor memory according to  claim 10 ,
   wherein gates of the third, fourth and fifth MOSFET are coupled to a first signal line.     
     
     
       12. The semiconductor memory according to  claim 10 ,
   wherein the first sub amplifier further includes an eleventh MOSFET coupled between one line of the first sub common IO line pair and one line of the first main common IO line pair and a twelfth MOSFET coupled between the other line of the first sub common IO line pair and the other line of the first main common IO line pair,        wherein gates of the eleventh and twelfth MOSFETs are coupled to a second signal line.     
     
     
       13. The semiconductor memory according to  claim 12 ,
   wherein gates of the third, fourth, and fifth MOSFETs are coupled to a first signal line.     
     
     
       14. The semiconductor memory according to  claim 13 ,
   wherein when information stored in one of the plurality of first memory cells is read out, the third, fourth, and fifth MOSFETs are ON - state, and        wherein when information is written into one of the plurality of first memory cells, the eleventh and twelfth MOSFETs are ON - state.     
     
     
       15. The semiconductor memory according to  claim 10 , further comprising:
   a plurality of first sub word drivers each coupled between the first main word line and corresponding one of the plurality of first sub word lines;        a plurality of second sub word drivers each coupled between the second main word line and corresponding one of the plurality of second sub word lines;        a plurality of first sense amplifiers coupled between the plurality of first bit lines and the plurality of first switch circuits; and        a plurality of second sense amplifiers coupled between the plurality of second bit lines and the plurality of second switch circuits.     
     
     
       16. The semiconductor memory according to  claim 15 ,
   wherein each of the plurality of first sub word drivers has a first P - channel MOSFET whose source and drain are coupled between corresponding one of a plurality of third signal lines and corresponding one of the plurality of first sub word lines and a first N - channel MOSFET whose source and drain are coupled between corresponding one of the plurality of first sub word lines and the first potential.     
     
     
       17. The semiconductor memory according to  claim 15 ,
   wherein the first memory array is located in a first region, wherein the second memory array is located in a second region, wherein the plurality of first sense amplifiers, the plurality of first switch      circuits, and the first sub common IO line pair are located in a third region,      wherein the plurality of first sub word drivers are located in a fourth region overlapping the third region.     
     
     
       18. The semiconductor memory according to  claim 17 ,
   wherein the first sub amplifier is located in an overlapping region of the third and fourth region, and        wherein the first main common IO line pair is located in the fourth region.     
     
     
       19. The semiconductor memory according to  claim 15 ,
   wherein the first memory array further includes a plurality of third bit lines extending in the second direction,        wherein the second memory array further includes a plurality of fourth bit lines extending in the second direction,        wherein the semiconductor memory further comprises        a third sub common IO line pair extending in the first direction and coupled to the plurality of third bit lines and the plurality of fourth bit lines,        a second main common IO line pair extending in the second direction,        a third sub amplifier coupled between the third sub common IO line pair and the second main common IO line pair,        a plurality of third sense amplifiers coupled to the plurality of third bit lines and the plurality of fourth bit lines,        a plurality of third switch circuits coupled between the plurality of sense amplifier and the third sub common IO line pair.