Multiport RAM with programmable data port configuration

Abstract

A RAM with programmable data port configuration provides for programmable configuration of RAM data ports, and in the case of a multiport RAM, for independent programmable configuration of each data port. A single programmable RAM cell can be utilized in a variety of data port configurations, thereby reducing the number of combinations necessary in a standard cell library or gate array in implement the every possible configuration. In one embodiment of the invention, a dual port RAM is provided with a decoder, an input multiplexer and an output multiplexer for each data port. The input multiplexer for each data port provides several different selectable mappings of a RAM input word of varying sizes to the input bit lines of the respective data port. Similarly, the output multiplexer for each data port provides several different selectable mappings of the RAM output bit lines to the RAM output word. The decoder receives configuration programming bits to determine the appropriate size of the RAM input and output word for the respective port, and based on column addressing bits, outputs a select signal to select the appropriate mapping from the input and output multiplexers. Decoding circuitry is used during RAM write operations to disable those input bits not addressed.

1. A circuit for programmably configuring a data port having a fixed word length M, comprising:
 a multiplexer circuit coupled to a data port, said multiplexer circuit having a selectable electronic mapping between said data port and a second port of programmable word-length N where N is less than or equal to M, said multiplexer circuit responsive to a select signal; and  
 a decoder having a configuration input and an address input, said decoder generating said select signal.  
 
     
     
       2. The circuit for programmably configuring a data port of  claim 1  wherein M divided by N is a multiple of two. 
     
     
       3. The circuit for programmably configuring a data port of  claim 1  wherein said programmable word-length N is dependent on said configuration input. 
     
     
       4. The circuit for programmably configuring a data port of  claim 3  wherein said configuration input is received from a register having configuration bits stored therein. 
     
     
       5. The circuit for programmably configuring a data port of  claim 3  wherein said configuration input is received from a ROM having configuration bits stored therein. 
     
     
       6. The circuit for programmably configuring a data port of  claim 1  wherein said decoder selects an N-bit word from said M-bit data port based on said address input. 
     
     
       7. The circuit for programmably configuring a data port of  claim 1  wherein said multiplexer circuit comprises:
 an input multiplexer coupled to said data port and said select signal, said input multiplexer selectably configured to map input data words of word-length N from said second port into said data port; and  
 an output multiplexer coupled to said data port and said select signal, said output multiplexer selectably configured to map output data words of word-length M from said data port into said second port.  
 
     
     
       8. The circuit for programmably configuring a data port of  claim 1  wherein said data port is part of a memory circuit, and wherein said decoder further comprises:
 a decoding circuit coupled to said data port, wherein said decoding circuit is configured to selectively disable a write operation for a portion of said data port based on said configuration input and said address input.  
 
     
     
       9. A multiport RAM with programmable data port configuration, comprising:
 a first internal data port of fixed width M;  
 a second internal data port of fixed width N;  
 a first multiplexer circuit coupled to said first internal data port, said first multiplexer circuit having a selectable electronic mapping between said first internal data port and a first external data port of programmable width X where X is less than or equal to M, said first multiplexer circuit responsive to a first select signal;  
 a second multiplexer circuit coupled to said second internal data port, said second multiplexer circuit having a selectable electronic mapping between said second internal data port and a second external data port of programmable width Y where Y is less than or equal to N, said second multiplexer circuit responsive to a second select signal;  
 a first decoder having a first configuration input and a first address input, said first decoder generating said first select signal; and  
 a second decoder having a second configuration input and a second address input, said second decoder generating said second select signal.  
 
     
     
       10. The circuit  multiport RAM of  claim 9  wherein M divided by X is a multiple of two. 
     
     
       11. The circuit  multiport RAM of  claim 9  wherein said programmable width X is dependent on said first configuration input, and said programmable width Y is dependent on said second configuration input. 
     
     
       12. The circuit  multiport RAM of  claim 11  wherein said first configuration input and said second configuration input are received from at least one register having configuration bits stored therein. 
     
     
       13. The circuit  multiport RAM of  claim 11  wherein said first configuration input and said second configuration input are received from a ROM having configuration bits stored therein. 
     
     
       14. The circuit  multiport RAM of  claim 9  wherein said first decoder selects an X-bit word from said first internal data port based on said first address input, and said second decoder selects a Y-bit word from said second internal data port based on said second address input. 
     
     
       15. The circuit  multiport RAM of  claim 9  wherein said first multiplexer circuit comprises:
 an input multiplexer coupled to said first internal data port and said first select signal, said input multiplexer selectably configured to map input data words of width X from said first external data port into said first internal data port; and  
 an output multiplexer coupled to said first internal data port and said first select signal, said output multiplexer selectably configured to map output data words of width M from said first internal data port into said first external data port.  
 
     
     
       16. The circuit  multiport RAM of  claim 9  wherein said second multiplexer circuit comprises:
 an input multiplexer coupled to said second internal data port and said second select signal, said input multiplexer selectably configured to map input data words of width Y from said second external data port into said second internal data port; and  
 an output multiplexer coupled to said second internal data port and said second select signal, said output multiplexer selectably configured to map output data words of width N from said second internal data port into said second external data port.  
 
     
     
       17. The circuit  multiport RAM of  claim 9  wherein each of said first and second decoders further comprise:
 a decoding circuit coupled to a respective internal data port, wherein said decoding circuit is configured to selectively disable a write operation for a portion of said respective internal data port based on a respective configuration input and a respective address input.  
 
     
     
       18. The circuit  multiport RAM of  claim 9  wherein X and Y are independently programmable.