Structure of delta-sigma fractional type divider

Abstract

The present invention relates to a structure of a delta-sigma fractional type divider. The divider structure adds an external input value and an output value of a delta-sigma modulator to modulate a value of a swallow counter. Therefore, the present invention can provide a delta-sigma fractional type divider the structure is simple and that can obtain an effect of a structure of a delta sigma mode while having a wide-band frequency mixing capability.

1. A delta-sigma fractional type divider, comprising:
 a delta-sigma modulator for receiving a clock signal and a first digital value to perform a delta-sigma modulation, said first digital value being used to program a fractional ratio frequency of a frequency synthesizer;  
 a swallow adder group for receiving an output value of said delta-sigma modulator and a second digital value to add an integer dividing ratio of a swallow counter and said output value of said delta-sigma modulator, said second digital value being used to program an integer ratio frequency of the frequency synthesizer;  
 a program register group for storing an output value of said swallow adder group; and  
 a pulse swallow counter group having a dual modulus prescaler, a program counter and said swallow counter, for dividing an input frequency depending on said value stored by said program register group.  
 
     
     
       2. The delta-sigma fractional type divider as claimed in  claim 1 , wherein said swallow adder group comprises:
 a first adder for adding the integer dividing ratio of the swallow counter and a sign value; and  
 a second adder for adding the output value of said delta-sigma modulator and an output value of said first adder.  
 
     
     
       3. The delta-sigma fractional type divider as claimed in  claim 2 , wherein said sign value is the most significant bit of said first digital value used to program the fractional ratio frequency of the frequency synthesizer. 
     
     
       4. The delta-sigma fractional type divider as claimed in  claim 1 , wherein said program register group further comprises:
 a swallow register for storing said output value of said swallow adder group; and  
 a main division register for storing the integer dividing ratio.  
 
     
     
       5. A delta-sigma fractional type divider, comprising:
   a modulator configured to use a first digital value to program a fractional ratio frequency of a frequency synthesizer;        an adder group configured to use an output value of said modulator and a second digital value, said second digital value being used to program an integer ratio frequency of the frequency synthesizer;        a program register group configured to store an output value of said adder group; and        a counter group configured to divide an input frequency depending on said value stored by said program register group.     
     
     
       6. The delta- sigma fractional type divider as claimed in    claim 5   , wherein said adder group comprises:      a first adder operable to add an integer dividing ratio of a counter and a sign value; and        a second adder operable to add the output value of said modulator and an output value of said first adder.     
     
     
       7. The delta-sigma fractional type divider as claimed in  claim 6 , wherein said sign value is a most significant bit of said first digital value used to program the fractional ratio frequency of the frequency synthesizer. 
     
     
       8. The delta-sigma fractional type divider as claimed in  claim 5 , wherein said program register group further comprises:
   a register operable to store said output value of said adder group; and        a main division register operable to store the integer dividing ratio.     
     
     
       9. The delta-sigma fractional type divider as claimed in  claim 5  wherein said modulator is a delta-sigma modulator and wherein said second digital value represents an integer dividing ratio of a counter. 
     
     
       10. The delta-sigma fractional type divider as claimed in  claim 5  wherein the counter group comprises a dual modulus prescaler, a program counter and a counter, for dividing an input frequency depending on said value stored by said program register group. 
     
     
       11. A method for delta-sigma fractional type dividing comprising:
   receiving a clock signal and a first digital value to perform a delta-sigma modulation, said first digital value being used to program a fractional ratio frequency of a frequency synthesizer;        adding an integer dividing ratio of a counter and an output value of said modulator to produce a second output value;        receiving a second digital value to program an integer ratio frequency of the frequency synthesizer;        storing the second output value using a program register group; and        dividing an input frequency depending on said value stored by said program register group.     
     
     
       12. The method of  claim 11  wherein the adding an integer dividing ratio comprises:
   adding an integer dividing ratio of the counter and a sign value; and        adding the output value of said modulator and an output value of said adding an integer dividing ratio of the counter and a sign value.     
     
     
       13. The method of  claim 12 , wherein said sign value is a most significant bit of said first digital value used to program the fractional ratio frequency of the frequency synthesizer. 
     
     
       14. The method of  claim 11 , further comprising:
   storing said second output value in a register; and        storing the integer dividing ratio in a main division register.     
     
     
       15. The method of  claim 11  wherein said modulator is a delta-sigma modulator.