Variable address length compiler and processor improved in address management

Abstract

The present invention discloses a program converting unit for generating a machine language instruction from a source program for a processor that manages an N-bit address while processing M-bit data, N being greater than M, and such a processor that runs the converted program. The program converting unit comprising: a parameter holding unit for holding a data width and a pointer width designated by a user; the data width representing the number of bits of data used in the source program while the pointer width representing the number of bits of an address; and a generating unit for generating an instruction to manage the data width when a variable operated by the instruction represents the data, and for generating an instruction to manage the pointer width when a variable operated by the instruction represents the address.

1. A program converting unit for generating a machine language instruction from a source program for a microprocessor having an address width N and a data width M, N being greater than M, N and M being inputs to the program converting unit as specified by a user, the value of N depending on a program size of the source program, said program converting unit comprising:
 parameter holding means for holding  unit configured to hold a data width M and a pointer width N, said data width M representing the number of bits of data used in the source program, said pointer width N representing the number of bits of an address, said N and M being input by a user during an execution of the program converting unit, the value of N depending on the program size; and  
 generating means for generating  unit configured to generate an instruction to manage said data width M when a variable operated by said instruction represents the data, and for generating  to generate an instruction to manage said pointer width N when a variable operated by said instruction represents the address,  
 wherein the program converting unit generates a unique set of machine language instruction from the source program for each N specified by the user.  
 
     
     
       2. The program converting unit of  claim 1 , wherein said M is 16 and said N is in a range of integers from 17 to 31 inclusive, said N being determined depending on the program size as follows:
 N=17, when the program size≦128 Kbytes  
 N=18, when the program size≦256 Kbytes  
 N=19, when the program size≦512 Kbytes  
 N=20, when the program size≦1 Mbyte  
 N=21, when the program size≦2 Mbytes  
 N=22, when the program size≦4 Mbytes  
 N=23, when the program size≦8 Mbytes  
 N=24, when the program size≦16 Mbytes  
 N=25, when the program size≦32 Mbytes  
 N=26, when the program size≦64 Mbytes  
 N=27, when the program size≦128 Mbytes  
 N=28, when the program size≦256 Mbytes  
 N=29, when the program size≦512 Mbytes  
 N=30, when the program size≦1 Gbyte  
 N=31, when the program size≦2 Gytes.  
 
     
     
       3. The program converting unit of  claim 1 , wherein said generating means  unit includes:
 determining means for determining  unit configured to determine a kind of the machine language instruction, the machine language instruction including (1) an instruction to access to a memory, (2) an instruction to use a register, and (3) an instruction to use an immediate;  
 memory managing means for outputting  unit configured to output a direction, in case of the (1) instruction, to manage said data width as an effective memory-access width when a variable to be accessed represents the data, and to manage said pointer width as an effective memory-access width when said variable represents the address;  
 register managing means for outputting  unit configured to output a direction, in case of the (2) instruction, to manage said data width as an effective bit-width when a variable to be read/written from/into the register represents the data, and to manage said pointer width as the effective bit-width when said variable represents the address;  
 immediate managing means for outputting  unit configured to output a direction, in case of the (3) instruction, to manage said data width as the effective bit-width when said immediate represents the data, and to manage said pointer width as the effective bit-width when said immediate represents the address; and  
 code generating means for generating  unit configured to generate the machine language instruction in accordance with the directions from said memory managing means  unit, said register managing means  unit, and said immediate managing means  unit.  
 
     
     
       4. The program converting unit of  claim 3 , wherein said M is 16 and said N is an integer in a range of 17 to 31 inclusive. 
     
     
       5. The program converting unit of  claim 4 , wherein:
 said N is 24; and  
 said code generating means  unit generates an instruction for a 24-bit data operation when said pointer width is greater than 16 bits and less than 24 bits, and generates an instruction for a 16-bit data operation when said pointer width is 16 bits or less.  
 
     
     
       6. A program converting unit for generating a machine language instruction based on a source program for a processor that manages an N-bit address while processing M-bit data, N being greater than M, said program converting unit comprising:
 syntax analyzing means for analyzing  unit configured to analyze a syntax of the source program to convert the same into an intermediary language comprising intermediary instructions, and subsequently for judging whether or not each variable contained in said intermediary instruction represents data used in an address;  
 table generating means for generating  unit configured to generate a table for each variable in said intermediary instructions, said table holding a name together with a type of each variable, said type representing one of the data and the address;  
 parameter holding means for holding  unit configured to hold a data width and a pointer width, said pointer width designated by a user as an input during an execution of the program converting unit, said data width representing the number of bits of the data while said pointer width represents the number of bits of the address; and  
 generating means for generating  unit configured to generate an instruction to manage said data width when the variable in said intermediary instruction represents the data, and an instruction to manage said pointer width when said variable represents the address.  
 
     
     
       7. The program converting unit of  claim 6 , wherein said M is 16 and said N is an integer in a range of 17 to 31 inclusive. 
     
     
       8. The program converting unit of  claim 6 , wherein said generating means  unit includes:
 judging means for judging  unit configured to judge a kind of the machine language instruction, the machine language instruction including (1) an instruction to access to an memory, (2) an instruction to use a register, and (3) an instruction to use an immediate;  
 memory managing means for outputting  unit configured to output a direction, in case of the (1) instruction, to manage a corresponding bit-width held in said parameter holding means  unit as an effective memory-access width depending on the type of a variable to be accessed shown in said table;  
 register managing means for outputting  unit configured to output a direction, in case of the (2) instruction, to manage a corresponding bit-width held in said parameter holding means  unit as an effective bit-width depending on the type of a variable to be read/written from/in the register shown in said table;  
 immediate managing means for outputting  unit configured to output a direction, in case of the (3) instruction, to manage a corresponding bit-width held in said parameter holding means  unit for the immediate as an effective bit-width depending on the type of the immediate shown in said table; and  
 code generating means for generating  unit configured to generate the machine language instruction in accordance with the direction from said memory managing means  unit, said register managing means  unit, and said immediate managing means  unit.  
 
     
     
       9. The program converting unit of  claim 8 , said M is 16 and said N is an integer in a range of 17 to 31 inclusive. 
     
     
       10. The program converting unit of  claim 9 , wherein:
 said N is 24; and  
 said code generating means  unit generates an instruction for a 24-bit data operation when said pointer width is greater than 16 bits and less than 24 bits, and generates an instruction for a 16-bit data operation when said pointer width is 16 bits or less.  
 
     
     
       11. A program converting unit for generating a machine language instruction based on a source program for a processor that manages an N-bit address while processing M-bit data, N being greater than M, said program converting unit comprising:
 syntax analyzing means for analyzing  unit configured to analyze a syntax of the source program to convert the same into an intermediary language comprising intermediary instructions, and to subsequently for judging  judge whether or not each variable contained in said intermediary instructions represents data used in an address;  
 table generating means for generating  unit configured to generate a table for each variable in said intermediary instructions, said table holding a same together with a type of each variable, said type representing one of the data and the address;  
 parameter holding means for holding  unit configured to hold a data width and a pointer width designated by a user, said data width representing the number of bits of the data while said pointer width representing the number of bits of the address;  
 judging means for judging  unit configured to judge a kind of the machine language instruction, the machine language instruction including (1) an instruction to access to an memory, (2) an instruction to use a register, and (3) an instruction to use an immediate;  
 memory managing means for outputting  unit configured to output a direction, in case of the (1) instruction, to manage a corresponding bit-width held in said parameter holding means  unit as an effective memory-access width depending on the type of a variable to be accessed shown in said table;  
 register managing means for outputting  unit configured to output a direction, in case of the (2) instruction, to manage a corresponding bit-width held in said parameter holding means  unit as an effective bit-width depending on the type of a variable to be read/written from/in the register shown in said table;  
 immediate managing means for outputting  unit configured to output a direction, in case of the (3) instruction, to manage a corresponding bit-width held in said parameter holding means  unit for the immediate as an effective bit-width depending on the type of the immediate shown in said table; and  
 code generating means for generating  unit configured to generate the machine language instruction in accordance with the directions from said memory managing means  unit, said register managing means  unit, and said immediate managing means  unit.  
 
     
     
       12. The program converting unit of  claim 11 , wherein said code generating means  unit generates an instruction for a 24-bit data operation when said pointer width is greater than 16 bits and less than 24 bits, and generates an instruction for a 16-bit data operation when said pointer width is 16 bits or less. 
     
     
       13. A program converting unit for generating a machine language instruction from a source program for an embedded microprocessor series that manages an N-bit address while processing M-bit data, N being greater than M, N being an input to the program converting unit depending on a program size, said program converting unit comprising:
 parameter holding means for holding  unit configured to hold a data width M and a pointer width N, said data width M representing the number of bits of data used in source the program, said pointer width N representing the number of bits of an address, said N being input by a user during an execution of the program converting unit, the value of N depending on the program size;  
 generating means for generating  unit configured to generate an instruction to manage said data width M when a variable operated by said instruction represents the data, and for generating  to generate an instruction to manage said pointer width N when a variable operated by said instruction represents the address;  
 option directing means for holding  unit configured to hold a user's direction for an overflow compensation, an overflow being possibly caused by an arithmetic operation; and  
 compensate instruction generating means for generating  unit configured to generate a compensation instruction to compensate an overflow in accordance with a type of a variable used in the arithmetic operation, said compensation instruction being generated when an effective bit-width of a variable designated by an operand is shorter than a register of N-bit wide and the arithmetic operation instruction will possibly cause an overflow exceeding said effective bit-width; and  
 prohibition means for prohibiting  unit configured to prohibit a generation of a compensation instruction by the compensation instruction generating means  unit when the option directing means  unit is storing an indication denoting not to compensate, wherein the program converting unit converts the source program into one of a plurality of different machine language programs depending on the values of N and M.  
 
     
     
       14. The program converting unit of  claim 13 , wherein said M is 16 and said N is an integer in a range of 17 to 31 inclusive. 
     
     
       15. The program converting unit of  claim 13 , wherein said M is 32, and said N is an integer in a range of 33 to 63 inclusive. 
     
     
       16. The program converting unit of  claim 13 , wherein said compensate instruction generating means  unit includes:
 instruction judging means for judging  unit configured to judge an arithmetic operation instruction that will possibly cause an overflow for all the machine language instructions when said option instructing means  unit holds the user's direction for executing the overflow compensation;  
 variable judging means  unit, with respect to a variable in the arithmetic operation instruction judged by said instruction judging means, for judging  unit configured to judge an effective bit-width and whether said variable is signed or unsigned by referring to said table;  
 sign-extension instruction generating means for generating  unit configured to generate a compensation instruction in case of a signed variable, a logical value of a sign bit being filled into all bits higher than the effective bit-width in a register that is to store said signed variable by said step-extension compensation instruction; and  
 zero-extension instruction generating means for generating  unit configured to generate a zero-extension compensation instruction in case of an unsigned variable, a logical value “0” being filled into all bits higher than the effective bit width in a register that is to store said unsigned variable by said zero-extension compensation instruction.  
 
     
     
       17. The program converting unit of  claim 16 , wherein said generating means  unit includes:
 determining means for determining  unit configured to determine a kind of the machine language instruction, the machine language instruction including (1) an instruction to access to a memory, (2) an instruction to use a register, and (3) an instruction to use an immediate;  
 memory managing means for outputting  unit configured to output a direction, in case of the (1) instruction, to manage said data width as an effective memory-access width when a variable to be accessed represents the data, and to manage said pointer width as an effective memory-access width when said variable represents the address;  
 register managing means for outputting  unit configured to output a direction, in case of the (2) instruction, to manage said data width as an effective bit-width when a variable to be read/written from/into the register represents the data, and to manage said pointer width as the effective bit-width when said variable represents the address;  
 immediate managing means for outputting  unit configured to output a direction, in case of the (3) instruction, to manage said data width as the effective bit-width when said immediate represents the data, and to manage said pointer width as the effective bit-width when said immediate represents the address; and  
 code generating means for generating  unit configured to generate the machine language instruction in accordance with the directions from said memory managing means  unit, said register managing means  unit, and said immediate managing means  unit.  
 
     
     
       18. The program converting unit of  claim 17 , wherein said M is 16 and said N is an integer in a range of 17 to 31 inclusive. 
     
     
       19. The program converting unit of  claim 17 , wherein said M is 32, and said N is an integer in a range of 33 to 63 inclusive. 
     
     
       20. A program converting unit for generating a machine language instruction based on a source program for a processor that manages an N-bit address while processing M-bit data, N being greater than M, said program converting unit comprising:
 syntax analyzing means for analyzing  unit configured to analyze a syntax of the source program to convert the same into an intermediary language comprising intermediate instructions, and to subsequently for judging  judge whether or not each variable contained in said intermediary instruction represents data used in an address;  
 table generating means for generating  unit configured to generate a table for each variable in said intermediary instructions, said table holding a name together with a type of each variable, said type representing one of the data and the address, and one of signed and unsigned data;  
 parameter holding means for holding  unit configured to hold a data width and a pointer width designated by a user during an execution of the program converting unit, said data width representing the number of bits of the data, said pointer width representing the number of bits of the address;  
 option directing means for holding  unit configured to hold a user's direction for an overflow compensation, an overflow being possibly caused by an arithmetic operation;  
 generating means for generating  unit configured to generate an instruction to manage said data width when the variable in said intermediary instruction represents the data, and an instruction to manage said pointer width when said variable represents the address; and  
 compensate instructions generating means for generating  unit configured to generate a compensation instruction to compensate an overflow in accordance with a type of a variable used in the arithmetic operation,  
 said type being judged when said option directing means  unit holds the user's direction for executing the overflow compensation, said compensation instruction being generated when an effective bit-width of a variable designated by an operand is shorter than a register of N-bit wide and the arithmetic operation instruction will possibly cause an overflow exceeding said effective bit-width; and  
 prohibition means for prohibiting  unit configured to prohibit a generation of a compensation instruction by the compensate instruction generating means  unit when the option directing means  unit is storing an indication denoting not to compensate.  
 
     
     
       21. The program converting unit of  claim 28 , wherein said M is 16 and said N is an integer in a range of 17 to 31 inclusive. 
     
     
       22. The program converting unit of  claim 21 , wherein said M is 16 and said N is an integer in a range of 17 to 31 inclusive. 
     
     
       23. The program converting unit of  claim 21 , wherein said M is 32, and said N is an integer in a range of 33 to 63 inclusive. 
     
     
       24. The program converting unit of  claim 20 , wherein said M is 32, and said N is an integer in a range of 33 to 63 inclusive. 
     
     
       25. The program converting unit of  claim 20 , wherein said compensate instruction generating means  unit includes:
 instruction judging means for judging  unit configured to judge an arithmetic operation instruction that will possibly cause an overflow for all the machine language instructions when said option instructing means  unit holds the user's direction for executing the overflow compensation;  
 variable judging means  unit, with respect to a variable in the arithmetic operation instruction judged by said instruction judging means, for judging  unit configured to judge an effective bit-width and whether said variable is signed or unsigned by referring to said table;  
 sign-extension instruction generating means for generating  unit configured to generate a compensation instruction in case of a signed variable, a logical value of a sign bit being filled into all bits higher than the effective bit-width in a register that is to store said signed variable by said sign-extension compensation instruction; and  
 zero-extension instruction generating means for generating  unit configured to generate a zero-extension compensation instruction in case of an unsigned variable, a logical value “0” being filled into all bits higher than the effective bit width in a register that is to store said unsigned variable by said zero-extension compensation instruction.  
 
     
     
       26. The program converting unit of  claim 25 , wherein said generating means  unit includes:
 determining means for determining  unit configured to determine a kind of the machine language instruction, the machine language instruction including (1) an instruction to access to a memory, (2) an instruction to use a register, and (3) an instruction to use an immediate;  
 memory managing means for outputting  unit configured to output a direction, in case of the (1) instruction, to manage a corresponding bit-width held in said parameter holding means  unit as an effective memory-access width depending on the type of a variable to be accessed shown in said table;  
 register managing means for outputting  unit configured to output a direction, in case of the (2) instruction, to manage a corresponding bit-width held in said parameter holding means  unit as an effective bit-width depending on the type of a variable to be read/written from/in the register shown in said table;  
 immediate managing means for outputting  unit configured to output a direction, in case of the (3) instruction, to manage a corresponding bit-width held in said parameter holding means  unit for the immediate as an effective bit-width depending on the type of the immediate shown in said table; and  
 code generating means for generating  unit configured to generate the machine language instruction in accordance with the directions from said memory managing means  unit, said register managing means  unit, and said immediate managing means  unit.  
 
     
     
       27. A program converting unit for generating a machine language instruction based on a source program for a processor that manages an N-bit address while processing M-bit data, N being greater than M, said program converting unit comprising:
 syntax analyzing means for analyzing  unit configured to analyze a syntax of the source program to convert the same into an intermediary language comprising intermediary instructions, and to subsequently for judging  judge whether or not each variable contained in said intermediary instructions represents data used in an address;  
 table generating means for generating  unit configured to generate a table for each variable in said intermediary instructions, said table holding a name together with a type of each variable, said type representing one of the data and the address, and one of signed and unsigned data;  
 parameter holding means for holding  unit configured to hold a data width and a pointer width designated by a user during an execution of the program converting unit, said data width representing the number of bits of the data, said pointer width representing the number of bits of the address;  
 option directing means for holding  unit configured to hold a user's direction for an overflow compensation, an overflow being possibly caused by an arithmetic operation;  
 generating means for generating  unit configured to generate an instruction to manage said data width when the variable in said intermediary instruction represents the data, and an instruction to manage said pointer width when said variable represents the address;  
 compensate instruction generating means for generating  unit configured to generate a compensation instruction to compensate an overflow in accordance with a type of a variable used in the arithmetic operation, said type being judged when said option directing means  unit holds the user's direction for executing the overflow compensation, said compensation instruction being generated when an effective bit-width of a variable designated by an operand is shorter than a register of N-bit wide and the arithmetic operation instruction will possibly cause an overflow exceeding said effective bit-width; and  
 prohibition means for prohibiting  unit configured to prohibit a generation of a compensation instruction by the compensate instruction generating means  unit when the option directing means  unit is storing an indication denoting not to compensate, wherein said generating means  unit includes: 
 determining means for determining  unit configured to determine a kind of the machine language instruction, the machine language instruction including (1) an instruction to access to a memory, (2) an instruction to use a register, and (3) an instruction to use an immediate;  
 memory managing means for outputting  unit configured to output a direction, in case of the (1) instruction, to manage a corresponding bit-width held in said parameter holding means  unit as an effective memory-access width depending on the type of a variable to be accessed shown in said table;  
 register managing means for outputting  unit configured to output a direction, in case of the (2) instruction, to manage a corresponding bit-width held in said parameter holding means  unit as an effective bit-width depending on the type of a variable to be read/written from/in the register shown in said table;  
 immediate managing means for outputting  unit configured to output a direction, in case of the (3) instruction, to manage a corresponding bit-width held in said parameter holding means  unit for the immediate as an effective bit-width depending on the type of the immediate shown in said table; and  
 
 code generating means for generating  unit configured to generate the machine language instruction in accordance with the directions from said memory managing means  unit, said register managing means  unit, and said immediate managing means  unit, and wherein  
 said compensate instruction generating means  unit includes: 
 instruction judging means for judging  unit configured to judge an arithmetic operation instruction that will possibly cause an overflow for all the machine language instructions when said option instructing means  unit holds the user's direction for executing the overflow compensation;  
 determining means  unit, with respect to a variable in the arithmetic operation instruction determined by said instruction determining means, for determining  unit configured to determine an effective bit-width and whether said variable is signed or unsigned by referring to said table;  
 sign-extension instruction generating means for generating  unit configured to generate a compensation instruction in case of a singed variable, a logical value of a sign bit being filled into all bits higher than the effective bit-width in a register that is to store said signed variable by said sign-extension compensation instruction; and  
 zero-extension instruction generating means for generating  unit configured to generate a zero-extension compensation instruction in case of an unsigned variable, a logical value “0” being filled into all bits higher than the effective bit width in a register that is to store said unsigned variable by said zero-extension compensation instruction.  
 
 
     
     
       28. A processor for processing data in accordance with instructions in a program comprising:
 register means  unit including a plurality of register groups, each group being identical in bit-width while being different in types;  
 instruction decoding means for decoding  unit configured to decode an instruction to output register information including a register designated by an operand contained in a data-transfer instruction;  
 external-access-width control means for outputting  unit configured to output the number of effective bits as bit-width information indicating a bit-width of transmission data in accordance with a kind of a register group to which said designated register belongs; and  
 external-access executing means for executing  unit configured to execute data transfer between said designated register and an external memory in accordance with said register information and said bit-width information.  
 
     
     
       29. The process of  claim 28 , wherein said register means  unit includes:
 an address register group including a plurality of address registers holding addresses; and  
 a data register group including a plurality of data registers holding data.  
 
     
     
       30. The processor of  claim 29 , wherein:
 said external-access-width control means  unit, as the bit-width information, outputs a bit-width determined in accordance with the effective bit-width of the data used in the program when said register information represents the data registers, and outputs a bit-width determined in accordance with a sufficiently large address space for a program size and data area size of the program when said register information represents the address registers.  
 
     
     
       31. The processor of  claim 29 , wherein:
 the address registers and data registers in said register means  unit are all 24-bit wide;  
 said instruction decoding means  unit outputs information that represents one of the address register and the data register as the register information;  
 said external-access-width control means  unit outputs the bit-width information exhibiting 24 bits when the register information representing the address register, and outputs the bit-width information exhibiting 16 bits when the register information representing the data register; and  
 the external-access executing means  unit executes the data transfer three times and twice for the 24- and 16-bit-width information respectively for an 8-bit-width external memory, and for twice and once for the 24- and 16-bit-width information respectively for a 16-bit-width external memory.  
 
     
     
       32. The processor of  claim 31 , wherein said access executing means  unit includes: p 1  an address generating circuit for holding an address designated by the data-transfer instruction to output one of a byte address and a word address to the external memory;
 an output data buffer for holding write data designated by the data-transfer instruction to output the same one of per byte and per word to the external memory;  
 an input data buffer for holding data from read out from the external memory; and  
 a sequence circuit for outputting a byte address to said address generating circuit for an 8-bit-width external memory while controlling the number of times for the data-transfer in accordance with the bit-width information via the input/output data buffers with respect to the read/write data, for outputting a word address to said address generating circuit for a 16-bit-width external memory while controlling the number of times for the data-transfer in accordance with the bit-width information via the input/output data buffers with respect to the read/write data.  
 
     
     
       33. The processor of  claim 29 , wherein:
 the address registers and data registers in said register means  unit are all 32-bit wide;  
 said instruction decoding means  unit outputs register information indicating whether the instruction uses the address register or data register;  
 said external-access-width control means  unit outputs the bit-width information exhibiting 24 bits when the register information representing the address register, and outputs the bit-width information exhibiting 16 bits when the register information representing the data register; and  
 the external-access executing means  unit executes the data transfer three times and twice for the 24- and 16-bit-width information respectively for an 8-bit-width external memory, and for twice and once for the 24- and 16-bit-width information respectively for a 16-bit-width external memory.  
 
     
     
       34. The processor of  claim 33 , wherein said access executing means  unit includes:
 an address generating circuit for holding an address designated by the data-transfer instruction to output one of a byte address and a word address to the external memory;  
 an output data buffer for holding write data designated by the data-transfer instruction to output the data one of per byte and per word to the external memory;  
 an input data buffer for holding data read out from the external memory; and  
 a sequence circuit for controlling said address generating circuit to output the byte address for an 8-bit-width external memory while controlling the input and output data buffers to input and output the byte data to transfer the read/write data to the external memory in a matching number of times to the bit-width of the external memory, and for controlling said address generating circuit to output the word address for a 16-bit-width external memory while controlling the input and output data buffers to input and output the word data to transfer the read/write data to the external memory in a matching number of times for the bit-width of the external memory.  
 
     
     
       35. A processor for operating certain data in accordance with an instruction in a program, comprising:
 a first register means for holding  unit configured to hold N-bit data;  
 a second register means for holding  unit configured to hold N-bit data;  
 sign-extending means for extending  unit configured to extend said M-bit data to N bits by copying an MSB of said M-bit data in a direction of an upper order, M being less than N;  
 zero-extending means for extending  unit configured to extend said M-bit data to N bits by copying a value “0” in a direction of an upper order;  
 operating means for operating  unit configured to operate an arithmetic operation in accordance with an instruction;  
 instruction control means for decoding  unit configured to decode an instruction to zero-extend M-bit immediate data when said M-bit immediate data are to be stored in said first register means  unit by the decoded instruction and to sign-extend said M-bit immediate data when said M-bit immediate data are to be stored in said second register means  unit by the decoded instruction, said zero-extended and sign-extended N-bit immediate data being outputted in one of two methods, one method being to send the extended N-bit immediate data from their respective extending means  unit to their respective register means  unit directly, the other being to send the same via the operating means  unit to their respective register means  unit, with said instruction including an indication for storing in the first register means  unit and said instruction including an indication for storing in the second register means  unit being of two different kinds of instructions, both kinds of instructions having a same operation code but having different destination operands.  
 
     
     
       36. The processor of  claim 35 , wherein:
 said first register means  unit is a group of a plurality of address registers for storing addresses, and  
 said second register means  unit is a group of a plurality of register means for storing  unit configured to store data.  
 
     
     
       37. The processor of  claim 36 , wherein said N is 24 and said M is 16. 
     
     
       38. A processor for operating certain data in accordance with an instruction in a program, comprising:
 a first register means for holding  unit configured to hold N-bit data;  
 a second register means for holding  unit configured to hold N-bit data;  
 sign-extending means for extending  unit configured to extend said M-bit data to N bits by copying an MSB of said M-bit data in a direction of an upper order, M being less than N;  
 zero-extending means for extending  unit configured to extend said M-bit data to N bits by copying a value “0” in a direction of an upper order;  
 operating means for operating  unit configured to operate an arithmetic operation in accordance with an instruction;  
 instruction decoding means for decoding  unit configured to decode an instruction in the program to detect a first type instruction and a second type instruction, said first type instruction including an instruction to store M-bit immediate data into said first register means  unit, said second type instruction including an instruction to store said M-bit immediate data into said second register means  unit; and  
 control means for outputting  unit configured to output said M-bit immediate data to said zero-extending means  unit when the first instruction is detected, and for outputting said M-bit immediate data to said sign-extending means  unit when the second type instruction is detected, said zero-extended N-bit immediate data and sign-extended N-bit immediate data being outputted in one of two methods, one method being to send the extended N-bit immediate data from their respective extending means  unit to their respective register means  unit directly, the other being to send the same via the operating means  unit to their respective register means  unit, with said first-type instruction and said second-type instruction both having a same operation code but having different destination operands.  
 
     
     
       39. The processor of  claim 38 , wherein:
 said first register means  unit is a group of a plurality of address registers for storing addresses, and  
 said second register means  unit is a group of a plurality of register means for storing  unit configured to store data.  
 
     
     
       40. The processor of  claim 39 , wherein:
 said first type instruction includes a data-transfer instruction to store the M-bit immediate data to said first register means  unit, an add instruction to add a value in said first register and the M-bit immediate data, and a subtract instruction to subtract the M-bit immediate data from a value in said first register, and  
 said second type instruction includes a data-transfer instruction to store the M-bit immediate data to said second register means  unit, an add instruction to add a value in said second register and the M-bit immediate data, and a subtract instruction to subtract the M-bit immediate data from a value in said second register.  
 
     
     
       41. The processor of  claim 40 , wherein said N is 24 and said M is 16. 
     
     
       42. A data processing method for executing an instruction that includes an operation code to store M-bit immediate data in the N-bit first register and an N-bit second register, both M and N being integers, with M being less than N, said method comprising the steps of:
 decoding the instruction for selecting one of the first register and second register in accordance with an operand of the decoded instruction;  
 zero-extending said M-bit immediate data to N bits when said decoded instruction designates the first register, and sign-extending said M-bit immediate data to N bits when said decoded instruction designates the second register; and  
 storing extended N-bit immediate data to the designated register.  
 
     
     
       43. The method of  claim 42 , wherein
 said first register means  unit is a group of a plurality of address registers for storing addresses, and  
 said second register means  unit is a group of a plurality of register means for storing  unit configured to store data.  
 
     
     
       44. The method of  claim 43 , wherein said N is 24 and said M is 16. 
     
     
       45. A processor being one out of an embedded processor series of processors with different address bit widths, having an address bit width which can be input by a user in accordance with program size, comprising:
 memory means for storing  unit configured to store a program including an N-bit data arithmetic operation instruction and other instructions operating both N-bit and M-bit data, N being greater than M, as well as for storing a program including conditional branch instructions, transfer instructions for external memory and instructions using immediate data;  
 a first register means  unit including a plurality of registers for holding N-bit data;  
 a second register means  unit including a plurality of registers for holding N-bit data;  
 a program counter for holding an N-bit instruction address to output the same to said memory means  unit;  
 fetching means for fetching  unit configured to fetch an instruction from an external memory using the instruction address from said program counter;  
 instruction decoding means for decoding  unit configured to decode a fetched instruction;  
 executing means for executing  unit configured to execute all arithmetic operation instructions at N-bit length and for executing instructions operating both N-bit and M-bit data excluding the arithmetic operation instructions;  
 a plurality of flag storing means  unit, each for storing a corresponding flag group changed in response to different bit-widths data in accordance with an execution result of said executing means  unit;  
 flag selecting means for selecting  unit configured to select a certain flag group from said plurality of flag means  unit in accordance with a conditional branch instruction decoded by said instruction decoding means  unit;  
 branch judging means for judging  unit configured to judge whether a branching is taken or not with a reference to a flag group selected by said flag selecting means  unit;  
 sign-extending means for extending  unit configured to extend M-bit data to N bits by copying an MSB of said M-bit data in a higher order;  
 zero-extending means for extending  unit configured to extend M-bit data to N bits by filling a value “0” in a higher order;  
 compensation instruction control means for compensating  unit configured to compensate contents of said first register means  unit and said second register means  unit using said sign-extending means  unit and said zero-extending means  unit in accordance with a compensation instruction inserted after a machine language instruction for an arithmetic operation that will possibly cause an overflow, said machine language instruction being decoded by said instruction decoding means  unit;  
 external-access-width control means for outputting  unit configured to output bit-width information for transmission data in accordance with a type of said register means  unit to which a register indicated by register information belongs, said register information indicating one of said first and second register means  unit;  
 external-access executing means for executing  unit configured to execute a data transfer between the register and an external memory in accordance with said register information and bit-width information; and  
 immediate control means for outputting  unit configured to output M-bit immediate data to said zero-extending means  unit when a decoded instruction includes an instruction to store said M-bit immediate data in said first register means  unit, and for outputting said M-bit immediate data to said sign-extending means  unit when a decoded instruction includes an instruction to store said M-bit immediate in said second register means  unit, said zero-extended and sign-extended immediate data being sent to said first and second register means  unit respectively in two methods, one being to send the same directly to their respective register means  unit and the other being to send the same via said executing means  unit, 
 wherein said memory means  unit stores a program of a size which is up to 2 N  bytes.  
 
 
     
     
       46. The processor of  claim 45 , wherein said N is 24 and said M is 16. 
     
     
       47. A program converting unit for generating a machine language instruction from a source program, the machine language program being generated for a selected microprocessor in an embedded microprocessor series comprising a plurality of microprocessors, each of the plurality of microprocessors being able to process M-bit data and having a different address bit width N, said program converting unit comprising:
 parameter holding means for holding  unit configured to hold a data width M and a selected pointer width N, N and M being integers greater than zero and N being greater than M,  
 said data width M representing a bit-width of data used in the source program to be converted,  
 said pointer width N-representing an address bit-width to be used with the converted machine language program and being set by a user, depending on an estimated size of the object program after conversion, in order to identify selected microprocessor in the embedded microprocessor series; and  
 generating means for generating  unit configured to generate an instruction to manage said data width M when a variable operated by said instruction represents the data, and for generating  to generate an instruction to manage said pointer width N when a variable operated by said instruction represents the address.  
 
     
     
       48. A program converting unit for generating a machine language instruction from a source program, the machine language program being generated for a selected microprocessor in an embedded microprocessor series comprising a plurality of microprocessors, each of the plurality of microprocessors being able to process M-bit data and having a different address bit width N, said program converting unit comprising:
 parameter holding means for holding  unit configured to hold a data width M and a selected pointer width N, N and M being integers greater than zero and N being greater than M,  
 said data width M representing a bit-width of data used in the source program to be converted,  
 said pointer width N representing an address bit-width to be used with the converted machine language program and being set by a user, depending on an estimated size of the object program after conversion, in order to identify selected microprocessor in the embedded microprocessor series;  
 generating means for generating  unit configured to generate an instruction to manage said data width M when a variable operated by said instruction represents the data, and for generating  to generate an instruction to manage said pointer width N when a variable operated by said instruction represents the address;  
 option directing means for holding  unit configured to hold a user's direction for an overflow compensation, an overflow being possibly caused by an arithmetic operation;  
 compensate instruction generating means for generating  unit configured to generate a compensation instruction to compensate an overflow in accordance with a type of a variable used in the arithmetic operation, said compensation instruction being generated when an effective bit width of a variable designated by an operand is shorter than a register of N-bit wide and the arithmetic operation instruction will possibly cause an overflow exceeding said effective bit-width; and  
 prohibition means for prohibiting  unit configured to prohibit a generation of a compensation instruction by the compensation instruction generating means  unit when the option directing means  unit is storing an indication denoting not to compensate.  
 
     
     
       49. A computer system comprising a processor and a program converting unit, wherein
 said processor is one out of a series of embedded-type processors, each processor in the series having a different address bit width N, N being longer than a data width M, the address bit width N of said processor being selected in accordance with a program size,  
 said program converting unit generates a machine language instruction from a source program for a processor out of an embedded-type custom processor series which has an address width N in accordance with a necessary program size, and  
 said processor comprising: 
 memory means for storing  unit configured to store a program, the memory means  unit having a minimum storage capacity of 2 N  bytes to store the program and having N address lines, the program including an N-bit data arithmetic operation instruction and other instructions operating on both N-bit and M-bit data, N being greater than M; and  
 a processor core having an address bus of N bits which is equal in size to the number of address lines of the memory means  unit, the processor core being selected from a plurality of processor cores,  
 wherein the processor core includes: 
 a program counter for holding an N-bit instruction address to output an instruction at the N-bit address to the memory means  unit, the program counter having an N-bit address length which is equal in size to the number of address lines of the memory means  unit;  
 fetching means for fetching  unit configured to fetch an instruction from the memory means  unit using an N-bit instruction address from said program counter; and  
 executing means for executing  unit configured to execute all N-bit arithmetic operation instructions and for executing other instructions except for arithmetic operation instructions at one of N-bit length and M-bit length, the executing means  unit having N-bit length,  
 whereby an N-bit address is calculated by the N-bit arithmetic operation independently of a data bit-width, said data bit-width being M, and  
 said program converting unit comprises: 
 parameter holding means for holding  unit configured to hold a data width M and a pointer width N, said data width M representing the number of bits of data used in the source program, said pointer width N representing the number of bits of an address, said N and M being input by a user in accordance with program size; and  
 generating means for generating  unit configured to generate an instruction based on the source program to set the data width M as valid when a variable used in a machine language instruction to be generated is a variable showing data, and for generating  to generate an instruction to set the address width N as valid when a variable used in a machine language instruction to be generated is a variable representing an address,  
 wherein the program converting unit generates a unique set of machine language instructions from the source program for each N specified by the user.  
 
 
 
 
     
     
       50. The computer system of  claim 49 , wherein the processor further comprises:
 an address register group including a plurality of N-bit address registers;  
 a data register group including a plurality of N-bit data registers,  
 wherein said executing means  unit executes the N-bit and M-bit data operation instructions using the address registers, while executing the M-bit data operation instruction using data registers.  
 
     
     
       51. The computer system of  claim 50 , wherein:
 said N is 24 and said M is 16; and  
 said processor is installed in a 1-chip microcomputer, whereby said 1-chip microcomputer becomes suitable for running a program that utilizes a memory over 64 Kbytes for an operation with 16-bit data.  
 
     
     
       52. The computer system of  claim 51 , wherein the processor further comprises:
 compensating means for extending  unit configured to extend an effective bit-width of the data in one of the address registers and the data register to 24 bits;  
 wherein said compensating means  unit operates in accordance with a compensate instruction entered after a machine language instruction designating an arithmetic operation that will possibly cause an overflow.  
 
     
     
       53. The computer system of  claim 52 , wherein said compensating means  unit includes:
 a first extending unit for filling a logical value of a sign bit in all bits higher than the effective bit-width in a register; and  
 a second extending unit for filling a logical value “0” in all bits higher than the effective bit-width in a register.  
 
     
     
       54. The computer system of  claim 50 , wherein the processor further comprises:
 compensating means for extending  unit configured to extend an effective bit-width of the data in one of the address registers and the data register to N bits,  
 wherein said compensating means  unit operates in accordance with a compensate instruction entered after a machine language instruction designating an arithmetic operation that will possibly cause an overflow.  
 
     
     
       55. The computer system of  claim 54 , wherein said compensating means  unit includes:
 a first extending unit for filling a logical value of a sign bit in all bits higher than the effective bit-width in a register; and  
 a second extending unit for filling a logical value “0” in all bits higher than the effective bit-width in a register.  
 
     
     
       56. The computer system of  claim 49 , wherein the processor further comprises:
 an address register group including a plurality of N-bit address registers; and  
 a data register group including a plurality of M-bit data registers,  
 wherein said executing means  unit executes one of an N-bit data operation instruction and an M-bit data operation instruction using the address registers, while executing the M-bit data operation instruction using data registers.  
 
     
     
       57. The computer system of  claim 56 , wherein:
 said N is 24 and said M is 16; and  
 said processor is installed in a 1-chip microcomputer, wherein said 1-chip microcomputer becomes suitable for running a program that utilizes a memory over 64 Kbytes for an operation with 16-bit data.  
 
     
     
       58. The computer system of  claim 57 , wherein the processor further comprises:
 compensating means for extending  unit configured to extend an effective bit-width of the data in one of the address registers and the data register to 24 bits;  
 wherein said compensating means  unit operates in accordance with a compensate instruction entered after a machine language instruction designating an arithmetic operation that will possibly cause an overflow.  
 
     
     
       59. The computer system of  claim 58 , wherein said compensating means  unit includes:
 a first extending unit for filling a logical value of a sign bit in all bits higher than the effective bit-width in a register;  
 a second extending unit for filling a logical value “0” in all bits higher than the effective bit-width in a register.  
 
     
     
       60. The computer system of  claim 49  wherein the pointer width N and the data width M are input by a user during an execution of the program converting unit. 
     
     
       61. A computer system comprising a central processing unit and a software program compiler, wherein
 the central processing unit is one of a series of processing units, each processing unit having a different address length N, N being longer than a data width M, the address length of the processing unit selected based on a size of a source program, the processing unit comprising: 
 memory means for storing  unit configured to store a program, the memory means  unit having a minimum storage capacity of 2 N  bytes to store the program and having N address lines, the program including an N-bit data arithmetic operation instruction and other instructions operating on both N-bit and M-bit data, N being greater than M; and  
 a processor core having an address bus of N bits which is equal in size to the number of address lines of the memory means  unit, the processor core being selected from a plurality of processor cores,  
 wherein the processor core includes: 
 a program counter for holding an N-bit instruction address to output an instruction at the N-bit address to the memory means  unit, the program counter having an N-bit address length which is equal in size to the number of address lines of the memory means  unit;  
 fetching means for fetching  unit configured to fetch an instruction from the memory means  unit using an N-bit instruction address from said program counter; and  
 executing means for executing  unit configured to execute all N-bit arithmetic operation instructions and for executing other instructions except for arithmetic operation instructions at one of N-bit length and M-bit length, the executing means  unit having N-bit length,  
 compensating means for extending  unit configured to extend an effective bit-width of the data in one of the address registers and the data register to N bits, wherein the compensating means  unit compensates as directed by a compensate instruction which is entered after a machine language arithmetic instruction which may cause an overflow;  
 whereby an N-bit address is calculated by the N-bit arithmetic operation independently of a data bit-width, said data bit-width being M, and the software compiler comprises: 
 parameter holding means for holding  unit configured to hold a data width M and a pointer width N, said data width M representing the number of bits of data used in the source program, said pointer width N representing the number of bits of an address, N and M being inputs to the compiler input by a user during an execution of the compiler, N and M selected by the user based on the size of the source program, and  
 generating means for generating  unit configured to generate an instruction based on the source program to set the data width M as valid when a variable used in a machine language instruction to be generated is a variable showing data, and for generating  to generate an instruction to set the address width N as valid when a variable used in a machine language instruction to be generated is a variable representing an address,  
 wherein the program converting unit generates a unique set of machine language instructions from the source program for each N specified by the user.