Structure for transistor devices in an SRAM cell

Abstract

An SRAM memory cell having first and second transfer gate transistors. The first transfer gate transistor includes a first source/drain connected to a bit line and the second transfer gate transistor has a first source/drain connected to a complement bit line. Each transfer gate transistor has a gate connected to a word line. The SRAM memory cell also includes first and second pull-down transistors configured as a storage latch. The first pull-down transistor has a first source/drain connected to a second source/drain of said first transfer gate transistor; the second pull-down transistor has a first source/drain connected to a second source/drain of said second transfer gate transistor. Both first and second pull-down transistors have a second source/drain connected to a power supply voltage node. The first and second transfer gate transistors each include a gate oxide layer having a first thickness, and the first and second pull-down transistors each include a gate oxide layer having a second thickness, wherein and the first thickness is different from the second thickness.

1. An SRAM memory cell comprising:
 a  first and second transfer gate transistors, the first transfer gate transistor having a first source/drain connected to a bit line and the second transfer gate transistor having a first source/drain connected to a complement bit line and each transfer gate transistor having a gate connected to a word line; and 
 first and second pull-down transistors configured as a storage latch, the first pull-down transistor having a first source/drain connected to a second source/drain of said first transfer gate transistor and the second pull-down transistor having a first source/drain connected to a second source/drain of said second transfer gate transistor, both first and second pull-down transistors having a second source/drain connected to a power supply voltage node; and  
 wherein the first and second transfer gate transistors each have a first width and include a gate oxide layer having a first thickness, the first and second pull-down transistors each have a second width and include a gate oxide layer having a second thickness, and a product of the first  second width and the first thickness is greater than or equal to a product of the second  first width and the second thickness.  
 
     
     
       2. The SRAM memory cell of  claim 1 , wherein the first thickness is thicker than the second thickness. 
     
     
       3. The SRAM memory cell of  claim 2 , wherein the first thickness is greater than two times the second thickness. 
     
     
       4. The SRAM memory cell of  claim 1 , wherein the first and second thicknesses are determined as follows: 
           [     [               ⁢   RATIO     ≤         Tox   tg       Tox   pd       ⁢         W   pd     /     L   pd           W   tg     /     L   tg         ⁢       Vcc   -     Vt   tg         Vcc   -     Vt   pd         ⁢         ]     ⁢         ]           
       RATIO   ≤         Tox   tg       Tox   pd       ⁢         W   pd     /     L   pd           W   tg     /     L   tg         ⁢       Vcc   -     Vt   pd         Vcc   -     Vt   tg               
 
       where RATIO is the desired ratio of the transfer gate transistors and the pull-down transistors, Tox tg  is the gate oxide thickness of the transfer gate transistor, Tox pd  is the gate oxide thickness of the pull-down transistor, W pd  is width of the pull-down transistor, L pd  is the length of the pull-down transistor, W tg  is the width of the transfer gate transistor, L tg  is the length of the transfer gate transistor, Vt tg  is the threshold voltage of the transfer gate transistor, and Vt pd  is the threshold voltage of the pull-down transistor. 
     
     
       5. The SRAM memory cell of  claim 4 , wherein RATIO is equal to 2.6. 
     
     
       6. A semiconductor circuit comprising:
 a first transistor having a first width and a first gate including a gate oxide layer having a first thickness; and  
 a second transistor having a second width and a second gate including a gate oxide layer having a second thickness, wherein a product of the second  first width and the second thickness is greater than a product of the first  second width and the first thickness.  
 
     
     
       7. The semiconductor circuit of  claim 6 , wherein the first transistor is a pull-down transistor in an SRAM memory cell. 
     
     
       8. The semiconductor circuit of  claim 7 , wherein the second transistor is a transfer gate transistor in the SRAM memory cell. 
     
     
       9. The semiconductor circuit of  claim 8 , wherein the gate oxide thickness of the pull-down transistor and a transfer gate transistor in the SRAM memory cell are selected using the following: 
           [     [               ⁢   RATIO     ≤         Tox   tg       Tox   pd       ⁢         W   pd     /     L   pd           W   tg     /     L   tg         ⁢       Vcc   -     Vt   tg         Vcc   -     Vt   pd         ⁢         ]     ⁢         ]           
       RATIO   ≤         Tox   tg       Tox   pd       ⁢         W   pd     /     L   pd           W   tg     /     L   tg         ⁢       Vcc   -     Vt   pd         Vcc   -     Vt   tg               
 
       where RATIO is the desired ratio of the transfer gate transistors and the pull-down transistors, Tox tg  is the gate oxide thickness of the transfer gate transistor, Tox pd  is the gate oxide thickness of the pull-down transistor, W pd  is width of the pull-down transistor, L pd  is the length of the pull-down transistor, W tg  is the width of the transfer gate transistor, L tg  is the length of the transfer gate transistor, Vt tg  is the threshold voltage of the transfer gate transistor, and Vt pd  is the threshold voltage of the pull-down transistor. 
     
     
       10. The semiconductor circuit of  claim 9 , wherein RATIO is at least 2.6. 
     
     
       11. The semiconductor circuit of  claim 10 , wherein the pull-down transistor is an n-channel field effect devices. 
     
     
       12. The semiconductor circuit of  claim 10 , wherein the transfer gate transistor is an n-channel field effect device. 
     
     
       13. A semiconductor circuit, comprising:
   a first transistor including a first gate having a first width and including a first gate insulator having a first thickness; and        a second transistor including a second gate having a second width and including a second gate insulator having a second thickness, a product of the first width and the second thickness being greater than or equal to a product of the second width and the first thickness.     
     
     
       14. The semiconductor circuit of  claim 13  wherein the first transistor comprises a pull- down transistor.   
     
     
       15. The semiconductor circuit of  claim 13  wherein the second transistor comprises a transfer gate transistor. 
     
     
       16. The semiconductor circuit of  claim 13  wherein the product of the first width and the second thickness is greater than the product of the second width and the first thickness. 
     
     
       17. A semiconductor circuit, comprising:
   a first transistor including a first channel region having a first width and including a first gate insulator having a first thickness; and        a second transistor including a second channel region having a second width and including a second gate insulator having a second thickness, a product of the first width and the second thickness being greater than or equal to a product of the second width and the first thickness.     
     
     
       18. The semiconductor circuit of  claim 17  wherein the first transistor comprises a pull- down transistor.   
     
     
       19. The semiconductor circuit of  claim 17  wherein the second transistor comprises a transfer gate transistor. 
     
     
       20. The semiconductor circuit of  claim 17  wherein the product of the first width and the second thickness is greater than the product of the second width and the first thickness. 
     
     
       21. A memory cell, comprising:
   a pull - down transistor including a first gate having a first width and including a first gate insulator having a first thickness; and        a transfer gate transistor coupled to the pull - down transistor and including a second gate having a second width and including a second gate insulator having a second thickness, a product of the first width and the second thickness being greater than or equal to a product of the second width and the first thickness.     
     
     
       22. A memory cell, comprising:
   a pull - down transistor including a first channel region having a first width and including a first gate insulator having a first thickness; and        a transfer gate transistor including a second channel region having a second width and including a second gate insulator having a second thickness, a product of the first width and the second thickness being greater than or equal to a product of the second width and the first thickness.