Method and apparatus for automatic pixel clock phase and frequency correction in analog to digital video signal conversion

Abstract

A methodAn apparatus and system for producing a digital video signal from an analog video signal, the analog video signal including an analog video data signal that is raster scanned in lines across a CRT screen to form consecutive frames of video information, the raster scanning controlled by use of a horizontal synchronizing signal (H snyc )( H sync ) that controls a line scan rate, and a vertical synchronizing signal (V snyc )( V sync ) that controls a frame refresh rate, to produce consecutive frames of video information, wherein the digital signal is produced by generating a pixel clock signal with pixel clocks for repetitively sampling instantaneous values of the analog video data signal, and digitizing the analog video data signal based on the pixel clock sampling. An expected width E, measured in number of pixel clocks, of a video image producible by the analog video signal is estimated, and an actual width W, measured in number of pixel clocks, of the video image producible by the analog video signal is calculated. The actual width W is compared with the expected width E. When E does not equal W, at least one of a frequency component and a phase component of the pixel clock signal is adjusted until E equals W.

1. A method for recovering a correct phase and frequency clock for an analog video signal that is converted for display on a digital display object having pixels arranged in lines and columns, the analog video signal including an analog video data signal that is operable for raster scanning in lines across a CRT screen to form consecutive frames of video information, the raster scanning controlled by timing signals that control a line scan rate and a frame refresh rate, to produce consecutive frames of video information, comprising the steps of:
 converting an analog video signal to a digital video signal;    estimating an expected width of an image producible by the analog video signal;    determining an actual width of a image producible by the digital video signal;    iteratively adjusting the digital video signal until the actual width equals the expected width.    
     
     
       2. The method of  claim 1 , including the steps of:
 generating a pixel clock signal that samples the analog video signal in order to convert the analog video signal to the digital video signal; and    iteratively adjusting at least one of frequency and phase of the pixel clock signal in order to iteratively adjust the digital video signal.    
     
     
       3. The method of  claim 2 , including the step of:
 adjusting the frequency of the pixel clock signal before adjusting the phase of the pixel clock signal.    
     
     
       4. The method for producing a digital video signal from an analog video signal, the analog video signal including an analog video data signal that is operable for raster scanning in lines across a CRT screen to form consecutive frames of video information, the raster scanning controlled by timing signals that control a horizontal line scan rate and a frame refresh rate, to produce consecutive frames of video information, comprising the steps of:
 generating a pixel clock signal with pixel clocks for repetitively sampling instantaneous values of the analog video data signal;    digitizing the analog video data signal based on the pixel clock sampling;    estimating an expected width E, measured in number of pixel clocks, of an expected video image producible by the analog video signal;    calculating an actual width W, measured in number of pixel clocks, of an actual video image producible by the analog video signal;    comparing the actual width W with the expected width E, and when E is unequal to W;    automatically adjusting at least one of a frequency component and a phase component of the pixel clock signal until E equals W.    
     
     
       5. The method of  claim 4 , including the steps of:
 automatically determining whether a phase difference exists between the pixel clock signal and the analog video data signal; and    automatically shifting the pixel clock phase to substantially eliminate the phase difference.    
     
     
       6. The method of  claim 4 , wherein the actual width W is equal to an actual number of pixel clocks from an actual left-most active pixel clock in a frame that reads a left-most actual active portion of the analog video data signal in the frame, to an actual right-most pixel clock in the frame that reads a right-most actual active portion of the analog video data signal in the frame. 
     
     
       7. The method of  claim 6 , wherein the expected width E is equal to an expected number of pixel clocks from an expected left-most pixel clock in the frame that reads an expected left-most active portion of the analog video data signal in the frame, to an expected right-most pixel clock in the frame that reads an expected right-most active value of the analog video data signal in the frame. 
     
     
       8. The method of  claim 7 , wherein the frequency component of the pixel clock signal is adjusted whenever one of W>E+1 and W<E holds true in the frame. 
     
     
       9. The method of  claim 7 , wherein the frequency component of the pixel clock signal is decreased whenever E<W−1. 
     
     
       10. The method of  claim 7 , wherein the frequency component of the pixel clock signal is increased whenever E>W. 
     
     
       11. The method of  claim 4 , wherein the frequency component of the pixel clock signal is adjusted by adjusting a number n of pixel clocks across each line in a frame of the analog video data signal. 
     
     
       12. The method of  claim 11 , wherein the number n of pixel clocks and the expected width E are determined by reference to a look-up table. 
     
     
       13. The method of  claim 4 , wherein the frequency component of the pixel clock signal is adjusted before the phase component of the pixel clock signal is adjusted. 
     
     
       14. The method of  claim 4 , wherein the phase of the pixel clock signal is adjusted by the steps:
 adjusting the pixel clock signal phase by a selected iterative amount for each of a series of subsequent frames until a frame phase error condition passes from W=E+1 through a subseries of frames where W=E, and back to a frame with a phase error condition of W=E+1;    storing the W values from the series of subsequent frames;    examining the W values to identify the subseries of consecutive frames in which W=E;    selecting a phase corrected frame in a center portion of the subseries of frames; and    setting the pixel clock phase at the phase of the phase corrected frame.    
     
     
       15. A method for recovering a correct phase and frequency clock for an analog video signal that is converted for display on a digital display object having pixels arranged in lines and columns, the analog video signal including an analog video data signal that is operable for raster scanning in lines across a CRT screen to form consecutive frames of video information, the raster scanning controlled by timing signals that control a line scan rate and a frame refresh rate, to produce consecutive frames of video information, comprising the steps of:
 generating a pixel clock signal that reads instantaneous values of the analog video data signal;    setting a total number n of pixel clocks that read the analog video data signal along each horizontal line;    determining an expected number E of pixel clocks from an expected left-most pixel clock in a frame that reads a left-most value of the analog video data signal that is greater than a selected threshold value, to an expected right-most pixel clock in the frame that reads a right-most value of the analog video data signal that is greater than the selected threshold value, the expected number E indicating an expected width of active analog video data;    determining an actual number W of pixel clocks from an actual left-most active pixel clock in the frame that reads a left-most actual value of the analog video data signal that is greater than the selected threshold value, to an actual right-most pixel clock in the frame that reads a right-most actual value of the analog video data signal that is greater than the selected threshold value, the actual member W indicating an actual width of active analog video data; and    comparing the actual number W with the expected number E.    
     
     
       16. The method of  claim 15 , including the steps of:
 when one of W>E+1 and W<E, calculating an adjusted total number n′ of pixel clocks that read instantaneous analog video data signal values across each line of analog video signal=n·(E/W);    substituting n′ for n for a next frame; and    redetermining the actual number W of pixel clocks for the next frame.    
     
     
       17. The method of  claim 15 , including the steps of:
 when W=E+1, adjusting pixel clock signal phase for a next frame; and    redetermining the actual number W of pixel clocks for the next frame.    
     
     
       18. The method of  claim 15 , including the steps of:
 when W=E+1, adjusting pixel clock signal phase by a selected iterative amount for each of a series of subsequent frames;    determining the actual number W of pixel clocks for each of the series of subsequent frames; and    storing the actual number W of pixel clocks for each of the series of subsequent frames;    identifying a subseries of consecutive frames in which W=E;    selecting a corrected frame from the subseries of consecutive frames, the corrected frame being from a middle portion of the subseries of consecutive frames;    identifying a corrected pixel clock signal phase of the corrected frame; and    setting the pixel clock signal phase to the corrected pixel clock signal phase.    
     
     
       19. The method of  claim 15 , including the step of correlating the expected width of the video image to an expected number E of pixel clocks. 
     
     
       20. The method of  claim 15 , including the step of correlating the actual width of the video image to an actual number W of activated pixels. 
     
     
       21. An apparatus comprising:
   a clock circuit to generate a pixel clock signal for converting an analog video signal into a digital video signal;        an edge detection circuit adapted to receive the digital video signal and to determine an actual width of an image produced by the digital video signal; and        a controller coupled to the clock circuit and the edge detection circuit to estimate an expected width of an image producible by the analog video signal and to facilitate the iterative adjustment of the pixel clock signal until the actual width equals the expected width.     
     
     
       22. The apparatus of  claim 21 , wherein the controller is adapted to receive a first timing signal associated with the analog video signal and to estimate the expected width of the image producible by the analog video signal based, at least in part, on the first timing signal. 
     
     
       23. The apparatus of  claim 22 , wherein the controller is adapted to receive a second timing signal associated with the analog video signal and to estimate the expected width of the image producible by the analog video signal based, at least in part, on the first and second timing signals. 
     
     
       24. The apparatus of  claim 23 , wherein the first and second timing signals correspond to a line scan rate and a frame refresh rate, respectively. 
     
     
       25. The apparatus of  claim 21 , wherein the edge detection circuit is coupled to the clock circuit to receive the pixel clock signal, said edge detection circuit to determine the actual width of the image produced by the digital video signal based at least in part on the pixel clock signal and the digital video signal. 
     
     
       26. The apparatus of  claim 21 , wherein the clock circuit comprises:
   a phase lock loop to generate the pixel clock signal based at least in part upon a horizontal synchronizing signal and a feedback signal; and        a programmable counter coupled to the phase lock loop to cooperatively generate a line advance signal and the feedback signal based at least in part upon a value n determined by the controller based upon the expected width of the image.     
     
     
       27. The apparatus of  claim 26 , wherein the clock circuit generates a line advance signal frequency corresponding to the horizontal synchronizing signal, and a pixel clock signal frequency corresponding to n times the line advance signal frequency. 
     
     
       28. The apparatus of  claim 21 , wherein the pixel clock signal comprises a frequency component and a phase component, and the controller is adapted to facilitate the iterative adjustment of the pixel clock signal by adjusting at least one component selected from a group consisting of the frequency component and the phase component. 
     
     
       29. The apparatus of  claim 28 , wherein the frequency component is adjusted prior to adjustment of the phase component. 
     
     
       30. The apparatus of  claim 28 , wherein the clock circuit further comprises:
   programmable delay logic to facilitate the adjustment of the phase component.     
     
     
       31. The apparatus of  claim 21 , wherein the controller comprises a processor. 
     
     
       32. The apparatus of  claim 21 , further comprising:
   an analog - to - digital converter, to receive the analog video signal and the pixel clock signal, and to convert the analog video signal to the digital video signal based at least in part on the pixel clock signal.     
     
     
       33. The apparatus of  claim 21 , wherein the edge detection circuit comprises:
   a pixel clock calculator adapted to receive the digital video signal and to determine a pixel value for each pixel clock pulse based, at least in part, on the digital video signal; and        comparison logic to compare the pixel values with a threshold value to determine whether a pixel clock pulse is active or inactive.     
     
     
       34. The apparatus of  claim 33 , wherein the edge detection circuit is adapted to determine the actual width based on the number of pixel clock pulses from a left- most active pixel clock pulse to a right - most active pixel clock pulse in a frame.   
     
     
       35. The apparatus of  claim 21 , wherein the edge detection circuit comprises an application specific integrated circuit. 
     
     
       36. A system comprising:
   an image capture circuit having      a clock circuit to generate a pixel clock signal for converting an analog video signal into a digital video signal; and        an edge detection circuit adapted to receive the digital video signal and to determine an actual width of an image produced by the digital video signal;          a controller, coupled to the image capture circuit, to estimate the expected width of an image producible by the analog video signal and to facilitate the iterative adjustment of the pixel clock signal until the actual width equals the expected width; and        a light valve controller, coupled to the image capture circuit, to receive the digital video signal and to transmit control signals to a light valve based at least in part on the digital video signal.     
     
     
       37. The system of  claim 36 , wherein the image capture circuit further comprises:
   an analog - to - digital converter adapted to receive the analog video signal from a multimedia source and the pixel clock signal from the clock circuit, and to transmit the digital video signal to the edge detection circuit and the light valve controller.     
     
     
       38. The system of  claim 36 , further comprising:
   a light source, to output light;        the light valve adapted to receive light from the light source and the control signals from the light valve controller, and to modulate the light based on the control signals; and        projection optics, coupled to receive the modulated light from the light valve and to project the image.     
     
     
       39. The system of  claim 38 , wherein the light valve comprises a liquid crystal display. 
     
     
       40. The system of  claim 38 , wherein the light valve comprises a digital micromirror device. 
     
     
       41. The system of  claim 36 , wherein the controller is adapted to receive a first timing signal associated with a line scan rate and a second timing signal associated with a frame refresh rate, and to estimate the expected width of the image based at least in part on the first and second timing signals. 
     
     
       42. The system of  claim 36 , wherein the clock circuit comprises
   a phase lock loop to generate the pixel clock signal based at least in part upon a horizontal synchronizing signal and a feedback signal; and        a programmable counter coupled to the phase lock loop to cooperatively generate a line advance signal and the feedback signal based at least in part upon a value n determined by the controller based upon the expected width of the image.     
     
     
       43. The system of  claim 42 , wherein the clock circuit generates a line advance signal frequency corresponding to the horizontal synchronizing signal, and a pixel clock signal frequency corresponding to n times the line advance signal frequency. 
     
     
       44. The system of  claim 36 , wherein the pixel clock signal comprises a frequency component and a phase component, and the controller is adapted to facilitate the iterative adjustment of the pixel clock signal by adjusting at least one component selected from a group consisting of the frequency component and the phase component.