Memory configuration of a composite memory device

Abstract

The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control a total system of the composite flash memory device and/or the only composite flash memory device in and sharing I/O line of the plural sector flash memory array, the read operation of the flash memory array is enable when the plural sector flash memory array is gained access.

1. A flash memory device comprising:
 a first flash memory array having a first predetermined number of blocks; and  
 a second flash memory array having a second predetermined number of blocks and sharing input/output lines with the first flash memory array, wherein the first predetermined number of blocks is different than the second predetermined number of blocks, wherein more than two of the blocks of the first flash memory array are minimum erasing units of the flash memory device, and wherein a read portion is enabled in the first  second flash memory array when the second  first flash memory array is written or erased.  
 
     
     
       2. The flash memory device as recited in  claim 1 , wherein the first flash memory array stores data and the second flash memory array stores program. 
     
     
       3. The flash memory device as recited in  claim 1 , further comprising internal program/erase control circuitry for inputting to and erasing from the first and second flash memory arrays. 
     
     
       4. The flash memory device as recited in  claim 1 , wherein the first flash memory array and the second flash memory array may be erased electrically at block level. 
     
     
       5. A flash memory device comprising:
 a first flash memory array having a first number of blocks of storage capacity; and  
 a second flash memory array having a second number of blocks of storage capacity and sharing input/output lines with the first flash memory array, wherein the first number of blocks is different than the second number of blocks, wherein more than two of the blocks of the first flash memory array are minimum erasing units of the flash memory device, and wherein the first  second flash memory array is capable of being read when the second  first flash memory array is written or erased.  
 
     
     
       6. The flash memory device as recited in  claim 5 , further comprising internal program/erase control circuitry for inputting to and erasing from the first and second flash memory arrays. 
     
     
       7. The flash memory device as recited in  claim 5 , wherein the first flash memory array and the second flash memory array may be erased electrically at block level. 
     
     
       8. A flash memory including an array of blocks divided into multiple areas, said flash memory comprising:
 a first flash memory area having a first number of blocks; and  
 a second flash memory area having a second number of blocks and sharing input/output lines with the first flash memory area, wherein the first number of blocks is different than the second number of blocks, wherein more than two of the blocks of the first flash memory array are minimum erasing units of the flash memory device, and wherein while programming or erasing in the second  first flash memory area, read operations are possible in the first  second flash memory area.  
 
     
     
       9. The flash memory as recited in  claim 8 , further comprising internal program/erase control circuitry for inputting to and erasing from the first and second flash memory area. 
     
     
       10. The flash memory as recited in  claim 8 , wherein the first flash memory area and the second flash memory area may be erased electrically at block level. 
     
     
       11. A flash memory device comprising:
 a first flash memory area;  
 a first X decoder and a first Y decoder for selecting a word line and a data line based on an input address, for controlling access to and from the first flesh memory area;  
 a first latch for latching data being input to or output from the first flash memory area  
 a second flash memory area;  
 a second X decoder and a second Y decoder for selecting a word line and a data line based on the input address, for controlling access to and from the first flesh memory area;  
 a second latch for latching data being input to or output from the second flash memory area, the first and second latches controlling a flow of data to and from input/output lines; and  
 a common address latch for latching address data to the first X decoder and the first Y decoder and to the second X decoder and the second Y decoder.  
 
     
     
       12. The flash memory device as recited in  claim 11 , wherein while programming or erasing in the second  first flash memory area, read operations are possible in the first  second flash memory area. 
     
     
       13. A flash memory device comprising:
 a first flash memory array having a first predetermined number of sectors; and  
 a second flash memory array having a second predetermined number of sectors and sharing input/output lines with the first flash memory array, wherein the first predetermined number of sectors is different than the second predetermined number of sectors, wherein more than two of the sectors of the first flash memory array are minimum erasing units of the flash memory device, and wherein a read operation is enabled in the first  second flash memory array when the second  first flash memory array is written or erased.  
 
     
     
       14. The flash memory device as recited in  claim 13 , wherein the first flash memory array stores data and the second flash memory array stores program. 
     
     
       15. The flash memory device as recited in  claim 13 , further comprising internal program/erase control circuitry for inputting to and erasing from the first and second flash memory arrays. 
     
     
       16. The flash memory device as recited in  claim 1 , wherein the first flash memory array and the second flash memory array may be erased electrically at sector level. 
     
     
       17. A flash memory device comprising:
 a first flash memory array having a first number of sectors of storage capacity; and  
 a second flash memory array having a second number of sectors of storage capacity and sharing input/output lines with the first flash memory array, wherein the first number of sectors is different than the second number of sectors, wherein more than two of the sectors of the first flash memory array are minimum erasing units of the flash memory device, and wherein the first  second flash memory array is capable of being read when the second  first flash memory array is written or erased.  
 
     
     
       18. The flash memory device as recited in  claim 17 , further comprising internal program/erase control circuitry for inputting to an erasing from the first and second flash memory arrays. 
     
     
       19. The flash memory device as recited in  claim 17 , wherein the first flash memory array and the second flash memory array may be erased electrically at sector level. 
     
     
       20. A flash memory including an array of storage divided into multiple areas, said flash memory comprising:
 a first flash memory area having a first number of sectors; and  
 a second flash memory area having a second number of sectors and sharing input/output lines with the first flash memory area, wherein the first number of sectors is different than the second number of sectors, wherein more than two of the sectors of the first flash memory array are minimum erasing units of the flash memory device, and wherein while programming or erasing in the second  first flash memory area, read operations are possible in the first  second flash memory area.  
 
     
     
       21. The flash memory as recited in  claim 20 , further comprising internal program/erase control circuitry for inputting to and erasing from the first and second flash memory areas. 
     
     
       22. The flash memory as recited in  claim 20 , wherein the first flash memory area and the second flash memory area may be erased electrically at sector level. 
     
     
       23. A flash memory device comprising:
 a first flash memory array having a first predetermined number of blocks; and  
 a second flash memory array having a second predetermined number of blocks and sharing input/output lines with the first flash memory array, wherein the first predetermined number of blocks is different than the second predetermined number of blocks, wherein more than two of the blocks of the first flash memory array are minimum erasing units of the flash memory device, and wherein an operation for reading from the second flash memory array is enabled by its respective enable line when the first flash memory array is accessed.  
 
     
     
       24. A flash memory device comprising:
 a first flash memory array having a first number of blocks of storage capacity; and  
 a second flash memory array having a second number of blocks of storage capacity and sharing input/output lines with the first flash memory array, wherein the first number of blocks is different than the second number of blocks, wherein more than two of the blocks of the first flash memory array are minimum erasing units of the flash memory device, and wherein an operation for reading from the second flash memory array is enabled by its respective enable line when the first flash memory array is accessed.  
 
     
     
       25. A flash memory including an array of blocks divided into multiple areas, said flash memory comprising:
 a first flash memory area having a first number of blocks; and  
 a second flash memory area having a second number of blocks and sharing input/output lines with the first flash memory area, wherein the first number of blocks is different than the second number of blocks, wherein more than two of the blocks of the first flash memory array are minimum erasing units of the flash memory device, and wherein an operation for reading from the second flash memory array is enabled by its respective enable line when the first flash memory array is accessed.  
 
     
     
       26. A flash memory device including:
 a first flash memory array having a first predetermined number of sectors; and  
 a second flash memory array having a second predetermined number of sectors and sharing input/output lines with the first flash memory array, wherein the first predetermined number of sectors is different than the second predetermined number of sectors, wherein more than two of the sectors of the first flash memory array are minimum erasing units of the flash memory device, and wherein an operation for reading from the second flash memory array is enabled by its respective enable line when the first flash memory array is accessed.  
 
     
     
       27. A flash memory device comprising:
 a first flash memory array having a first number of sectors of storage capacity; and  
 a second flash memory array having a second number of sectors of storage capacity and sharing input/output lines with the first flash memory array, wherein more than two of the sectors of the first flash memory array are minimum erasing units of the flash memory device, and wherein an operation for reading from the second flash memory array is enabled by its respective enable line when the first flash memory array is accessed.  
 
     
     
       28. A flash memory including an array of storage divided into multiple areas, said flash memory comprising:
 a first flash memory area having a first number of sectors; and  
 a second flash memory area having a second number of sectors and sharing input/output lines with the first flash memory area, wherein the first number of sectors is different than the second number of sectors, wherein more than two of the sectors of the first flash memory array are minimum erasing units of the flash memory device, and wherein an operation for reading from the second flash memory array is enabled by its respective enable line when the first flash memory array is accessed.  
 
     
     
       29. A flash memory device comprising:
 a first flash memory array having a first predetermined number of blocks; and  
 a second flash memory array having a second predetermined number of blocks and sharing input/output lines with the first flash memory array, wherein the first predetermined number of blocks is different than the second predetermined number of blocks, wherein each block is a minimum erasing unit of the flash memory device, and wherein an operation for reading from the second flash memory array is enabled by its respective enable line when the first flash memory array is accessed.  
 
     
     
       30. A flash memory device comprising:
 a first flash memory array having a first number of blocks of storage capacity; and  
 a second flash memory array having a second number of blocks of storage capacity and sharing input/output lines with the first flash memory array, wherein the first number of blocks is different than the second number of blocks, wherein each block is a minimum erasing unit of the flash memory device, and wherein an operation for reading from the second flash memory array is enabled by its respective enable line when the first flash memory array is accessed.  
 
     
     
       31. A flash memory including an array of blocks divided into multiple areas, said flash memory comprising:
 a first flash memory area having a first number of blocks; and  
 a second flash memory area having a second number of blocks and sharing input/output lines with the first flash memory area, wherein the first number of blocks is different than the second number of blocks, wherein each block is a minimum erasing unit of the flash memory device, and wherein an operation for reading from the second flash memory array is enabled by its respective enable line when the first flash memory array is accessed.  
 
     
     
       32. A flash memory device comprising:
 a first flash memory array having a first predetermined number of sectors; and  
 a second flash memory array having a second predetermined number of sectors and sharing input/output lines with the first flash memory array, wherein the first predetermined number of sectors is different than the second predetermined number of sectors, wherein each sector is a minimum erasing unit of the flash memory device, and wherein an operation for reading from the second flash memory array is enabled by its respective enable line when the first flash memory array is accessed.  
 
     
     
       33. A flash memory device comprising:
 a first flash memory array having a first number of sectors of storage capacity; and  
 a second flash memory array having a second number of sectors of storage capacity and sharing input/output lines with the first flash memory array, wherein the first number of sectors is different than the second number of sectors, wherein each sector is a minimum erasing unit of the flash memory device, and wherein an operation for reading from the second flash memory array is enabled by its respective enable line when the first flash memory array is accessed.  
 
     
     
       34. A flash memory including an array of storage divided into multiple areas, said flash memory comprising:
 first flash memory area having a first number of sectors; and  
 a second flash memory area having a second number of sectors and sharing input/output lines with the first flash memory area, wherein the first number of sectors is different than the second number of sectors, wherein each sector is a minimum erasing unit of the flash memory device, and wherein an operation for reading from the second flash memory array is enabled by its respective enable line when the first flash memory array is accessed.