Multi-phase locked loop for data recovery

Abstract

The present invention provides a multi-phase-locked loop without dead zone, which can reduce clock jitter and provide larger tolerance for data random jitter. It generates and output multiple sets of control signals (up k /dn k ) via a multi-phase voltage controlled oscillator which generates a plurality of multi-phase clock signals for detecting the transition edge of data signal. Therefore, the phase error θ e and the voltage Vd of the multi-phase-locked loop can be adjusted to be nearly linear according to the control signals. A multi-phase-locked loop without dead zone thus can be provided.

1. A multi-phase-locked loop for data recovery comprising a phase detector, a charge pump, a loop filter and a voltage controlled oscillator, wherein:
 said phase detector is constituted by N phase detection units (U 1 , U 2 , . . . , U N , N is even, N≧4); said N phase detection units are connected in cascade configuration, and each phase detection unit contains: 
 a data signal input terminal for receiving a data signal from outside;  
 a clock signal input terminal for receiving the  one of multi-phase clock signals (CK 1 , CK 2 , . . . , CK N ) from outside;  
 a delay signal input terminal for receiving a delay signal output from another phase detection unit;  
 a delay signal output terminal for outputting a delay signal of the phase detection unit; and  
 a charge/discharge control signal output terminal for outputting a control signals for charge/discharge operations;  
 
 each of said N phase detection units generates a delay signal (D 1 , D 2 , . . . , D N ) according to an input  the data signal and the complement of a  the multi-phase clock signal; the delay signal (D j+1 ) generated by the (j+1) th  phase detection unit is input into the j th  phase detection unit via the j th  delay signal input terminal; the delay signal (D 1 ) generated by the first phase detection unit is input into the N th  phase detection unit via the N th  delay signal input terminal;  
 the j th  phase detection unit (U j   ′ U   j , 1≦j<N, j is a positive integer) generates one of the control signals (dn 1 , dn 2 , . . . , dn N/2 , up N/2 , . . . , up 2 ) for charge/discharge operations according to the delay signal (D j ) from the j th  phase detection unit, the delay signal (D j+1 ) from the (j+1) th  phase detection unit, and the multi-phase clock signal (CK j ) which is applied to the j th  phase detection unit;  
 the N th  phase detection unit generates a charge control signal (up 1 ) according to the delay signal (D n ) from the N th  phase detection unit, the delay signal (D 1 ) from the first phase detection unit, and the multi-phase clock signal (CK N ) which is applied to the N th  phase detection unit;  
 said charge pump being constituted by N/2 charge and discharge units (CP 1 , CP 2 , . . . , CP N/2 ), wherein the k th  (CP k , 1≦k≦N/2) charge and discharge unit (CP k ) is employed to receive the k th  charge/discharge control signal set (up k /dn k ) from said phase detector, and a current Ich k  is generated by the charge/discharge control signal set (up k /dn k ); the charge/discharge current Ich k =(w k ×up k −w k ×dn k )Iss, wherein w k  is a weighting value, Iss is a fixed current value, and w 1 <w 2 < . . . <w N/2 ; the total charge/discharge current (Ich) from said charge pump equals to Ich 1 +Ich 2 + . . . Ich k + . . . +Ich N/2 ; and  
 said voltage controlled oscillator is a multi-phase voltage controlled oscillator, which outputs N multi-phase clock signals (CK 1 , CK 2  . . . , CK N ), which are applied to said phase detectors  phase detection units, respectively.  
 
     
     
       2. The multi-phase-locked loop for data recovery as described in  claim 1 , wherein the phase difference between the multi-phase clock signal (CK j+1 ) input to the (j+1) th  phase detection unit (U j+1 ) and the multi-phase clock signal (CK j ) input to the j e  phase detection unit (U j ) equals to 2π/N. 
     
     
       3. The multi-phase-locked loop for data recovery as described in  claim 1 , wherein each of said N phase detection unit comprises: an inverter, a first flip-flop, an exclusive OR gate, and a second flip-flop;
 said inverter inverting multi-phase clock signal which is to be input to each phase detection unit; the first flip-flop generating a delay signal according to the complementary multi-phase clock signal from said inverter and the data signal; the delay signal from said first flip-flop and the delay signal from the first flip-flop in another phase detection unit being input to the exclusive OR gate; the second flip-flop generating a charge/discharge control signal according to the multi-phase clock signal and the output signal from said exclusive OR gate.  
 
     
     
       4. The multi-phase-locked loop for data recovery as described in  claim 3 , wherein said first flip-flop and said second flip-flop are D flip-flops. 
     
     
       5. A multi- phase - locked loop comprising:      a phase detector configured to:      receive a data signal and a plurality of multi - phase clock signals;        detect a phase difference between the data signal and each multi - phase clock signal; and        output a plurality of control signals;          a charge pump, configured to receive the control signals and produce a total control current according to the control signals, the charge pump comprising a plurality of charge/discharge units, wherein at least one of charge/discharge units comprises a first current source, a second current source, and a switch module, and wherein each charge/discharge unit has a weighting value, and at least two of the weighting values are different;        a loop filter configured to receive the total control current and produce a control voltage according to the total control current; and        a voltage controlled oscillator  ( VCO )  configured to produce the multi - phase clock signals according to the control voltage, wherein the multi - phase clock signals are at substantially the same frequency.     
     
     
       6. The multi- phase - locked loop of    claim 5   , wherein the charge pump is controlled by the control signals such that the relation between the control voltage and the phase difference of the multi - phase - locked loop is adjusted to be nearly linear.   
     
     
       7. The multi- phase - locked loop of    claim 5   , wherein the control signals are maintained as a fixed time period such that a dead zone of the multi - phase - locked loop is reduced.   
     
     
       8. The multi- phase - locked loop of    claim 5   , wherein the control signals are maintained as a fixed time period such that jitter of the multi - phase clock signal is reduced.   
     
     
       9. A multi- phase - locked loop comprising:      a phase detector configured to:      receive a data signal and a plurality of multi - phase clock signals;        detect a phase different between the data signal and each multi - phase clock signal; and        output a plurality of control signals;          a charge pump, configured to receive the control signals and produce a total control current according to the control signals;        said charge pump including a first current source, a second current source, and a switch module;        a loop filter configured to receive the total control current and produce a control voltage according to the total control current; and        a voltage controlled oscillator  ( VCO )  configured to produce the multi - phase clock signals according to the control voltage, wherein the multi - phase clock signals are at substantially the same frequency, wherein the phase detector comprises N phase detection units  ( N is even, N>= 4   ) , the N phase detection units being coupled in cascade configuration.     
     
     
       10. The multi- phase - locked loop of    claim 9   , wherein a phase difference between a first multi - phase clock signal and a second multi - phase clock signal adjacent to the first multi - phase clock signal is  2 π/N.   
     
     
       11. The multi- phase - locked loop of    claim 9   , wherein each phase detection unit comprises:      a first flip - flop configured to generate a delay signal according to the corresponding multi - phase clock signal and the data signal;        an exclusive OR gate configured to receive the delay signal from the first flip - flop and another delay signal from another first flip - flop in another phase detection unit; and        a second flip - flop configured to output one of the plurality of control signals according to an output signal of the exclusive OR gate and the corresponding multi - phase clock signal.     
     
     
       12. The multi- phase - locked loop of    claim 11   , wherein the first flip - flop and the second flip - flop are D flip - flops.   
     
     
       13. The multi- phase - locked loop of    claim 5   , wherein each charge/discharge unit is configured to generate an output current according to the corresponding control signal,      wherein the charge pump is configured to receive the output currents and produce the total control current.     
     
     
       14. A phase detector for detecting phase differences between a data signal and a plurality of multi- phase clock signals and producing a plurality of control signals, wherein the frequencies of the multi - phase clock signals are substantially the same, the phase detector comprising:      a plurality of phase detection units, the phase detection units being coupled in cascade configuration, wherein each of the phase detection units comprises:      a first flip - flop configured to generate a delay signal according to the corresponding multi - phase clock signal and the data signal;        an exclusive OR gate configured to receive the delay signal from the first flip - flop and another delay signal from another first flip - flop in another phase detection unit; and        a second flip - flop configured to generate one of the plurality of control signals according to an output signal of the exclusive OR gate and the corresponding multi - phase clock signal.       
     
     
       15. The multi- phase - locked loop of    claim 5   , wherein the charge pump is configured to produce a plurality of output currents according to the control signals, and the charge pump is configured to produce the total control current according to the output currents.   
     
     
       16. The multi- phase - locked loop of    claim 15   , wherein each output current has a corresponding weighting value, and at least two of the weighting values are different.   
     
     
       17. The multi- phase - locked loop of    claim 15   , wherein the charge pump includes a plurality of switching devices controlled by the control signals, and the charge pump produces the output currents selectively through the switching devices.   
     
     
       18. The multi- phase - locked loop, comprising:      a phase detector configured to:      receive a data signal and a plurality of multi - phase clock signals;        detect a phase difference between the data signal and each multi - phase clock signal; and        output a plurality of control signals;          a charge pump, configured to receive the control signals and produce a total control current according to the control signals;        a loop filter configured to receive the total control current and produce a control voltage according to the total control current; and        a voltage controlled oscillator  ( VCO )  configured to produce the multi - phase clock signals according to the control voltage, wherein the multi - phase clock signals are at substantially the same frequency;        wherein the charge pump comprises a plurality of charge/discharge units, each charge/discharge unit has a corresponding weighting value, and at least two of the weighting values are different.     
     
     
       19. The multi- phase - locked loop of    claim 5   , wherein the phase detector comprises:      a plurality of phase detection units, the phase detection units being coupled in cascade configuration, wherein each of the phase detection units comprises:      a first flip - flop configured to generate a delay signal according to the corresponding multi - phase clock signal and the data signal;        a logic circuit configured to receive the delay signal from the first flip - flop and another delay signal from another first flip - flop in another phase detection unit; and          a second flip - flop configured to generate one of the plurality of control signals according to an output signal of the logic circuit and the corresponding multi - phase clock signal.