Integrated digital signal processor/general purpose CPU with shared internal memory

Abstract

An integrated data processing platform for processing a digital signal that includes a general purpose processor and a digital signal processor (DSP) module. The DSP module recovers digital data from a digital signal utilizing a sequence of DSP operations selected by the general purpose processor. The general purpose processor processes the digital data recovered by the DSP module, but is also available to perform general purpose tasks. A shared internal memory array selectively provides information to the DSP module and to the general purpose processor. The information stored in the internal memory array includes operands utilized in the execution of the DSP algorithm and selected instructions and data utilized by the general purpose CPU either for controlling the execution of the DSP algorithm or for executing its own general purpose tasks. While in many applications the data processing system will include an analog front end that converts a modulated input signal received on an analog transmission channel to a corresponding digital signal for processing by the data processing system, the data processing system may also receive the digital signal directly from a digital source.

1. A data processing system for processing a digital signal, the data processing system comprising:
 a shared bus for transferring both data and instructions;    a shared memory array for storing both data and general purpose instructions and that is connected for transfer of both data and general purpose instructions between the shared bus and the shared memory array;    a digital signal execution unit connected to the shared bus for processing the digital signal utilizing both data transferred between the shared memory array and the digital signal execution unit on the shared bus and a selected sequence of individual digital signal processor (DSP) instructions, the selected sequence of DSP instructions consisting of individual general purpose instructions transferred between the shared memory array and the digital signal execution unit on the shared bus; and    a general purpose processor connected to the shared bus for controlling the digital signal execution unit by selecting each general purpose instruction to be transferred to the digital signal execution unit from the shared memory array    whereby the selected sequence of individual DSP instructions executed by the digital signal execution unit is selectively configurable by the general purpose processor.    
     
     
       2. An integrated circuit data processing system for processing a digital signal, the data processing system comprising;
 a shared internal bus for transferring both general purpose instructions and data;    a shared bus interface unit connected to the shared internal bus and connectable via a shared external bus to a shared external memory array via an external input/output port of the shared external memory array such that general purpose instructions and data stored in the shared external memory array may be transferred via external input/output port to be shared internal bus via the shared bus interface unit;    a digital signal execution unit connected to the shared internal bus for processing the digital signal utilizing both data transferred to the digital signal execution unit from the shard external memory array via the shared internal bus and a selected sequence of individual digital signal processor (DSP) instructions, the selected sequence of DSP instructions consisting of individual general purpose instructions transferred to the digital signal execution unit from the shared external memory array via the shared internal bus; and    a general purpose processor connected to the shared internal bus for controlling the digital signal execution unit by selecting each of the general purpose instructions to be transferred to the digital signal execution unit from shared external memory array via the shared internal bus    whereby the selected sequence of individual DSP instructions executed by the digital signal execution unit is selectively configurable by the general purpose processor.    
     
     
       3. An integrated circuit data processing system as in  claim 2  and further comprising a shared internal memory array connected to the shared internal bus via an internal input/output port of the shared internal memory array such that general purpose instructions and data stored in the shared internal memory are transferred via the internal input/output port of the shared internal memory array to the shared internal bus for transfer to either the digital signal execution unit or the general purpose processor
 whereby the selected sequence of individual DSP instructions executed by the digital signal execution unit is selectively configurable by the general purpose processor selecting individual general purpose instructions from the shared external memory and/or the shared internal memory.    
     
     
       4. A data processing system for processing a digital signal, the data processing system comprising:
 a shared bus for transferring both data operands and general purpose instructions;    a shared memory array for storing both data operands and general purpose instructions and that is connected for transfer of data operands and general purpose instructions between the shared bus and the shared memory array;    a digital signal execution unit connected to the shared bus for processing the digital signal utilizing data operands transferred from the shared memory array to the digital signal execution unit on the shared bus and a selected sequence of individual digital signal processor (DSP) instructions, the selected sequence of DSP instructions consisting of individual general purpose instructions transferred from the shared memory array to the digital signal execution unit on the shared bus; and    a general purpose processor connected to the shared bus for controlling the digital signal execution unit by selecting each general purpose instruction to be transferred to the digital signal execution unit from the shared memory array; and    wherein the digital signal execution unit includes    a control register connected to the shared bus for storing a general purpose instruction transferred to the digital signal execution unit by the general purpose processor from the shared memory array on the shared bus;    a multiply/accumulate unit that responds to storage of said general purpose instruction in the control register by initiating execution of a DSP operation corresponding to said general purpose instruction; and    a DSP address generator connected to the shared bus for retrieving a first data operand stored in the shared memory and utilizable by the multiply/accumulate unit in executing said DSP operation.    
     
     
       5. A data processing system as in  claim 4  wherein the multiply/accumulate unit includes first and second input ports for receiving said first data operand and a second data operand respectively, for utilization by the multiply/accumulate unit in executing said DSP operation. 
     
     
       6. A data processing system as in  claim 5  wherein the address generator includes means for retrieving both said first data operand and said second data operand from the shared memory array via the shared bus. 
     
     
       7. An integrated circuit data processing system for processing a digital signal, the data processing system comprising:
 (a) a digital signal execution unit that recovers digital data from the digital signal by executing a selected sequence of digital signal processor (DSP) instructions;    (b) a general purpose processor that selects the sequence of DSP instructions for execution by the digital signal execution unit from a set of DSP instructions and that performs general purpose processing tasks by executing general purpose instructions utilizing selected data;    (c) a shared internal bus for transferring both data and instructions and to which both the digital signal execution unit and the general purpose processor are connected; and    (d) a shared internal memory array connected to the shared internal bus via an internal input/output port of the shared internal memory array such that the shared internal memory array is accessible by the digital signal execution unit via the internal input/output port for transferring operands utilizable by the digital signal execution unit between the shared internal memory array and the digital signal execution unit on the shared internal bus and such that the shared internal memory array is accessible by the general purpose processor via the internal input/output port for transferring the general purpose instructions and the selected data between the shared internal memory array and the general purpose processor on the shared internal bus; and    (e) a shared bus interface unit connected between the shared internal bus and a shared external system memory that stores operands, instructions and data for implementing the transfer of operands, instructions and data between the shared internal bus and the shared external system memory such that the digital signal execution unit and the general purpose processor may access either the shared internal memory via the internal input/output port of the shared internal memory or the shared external memory system via the shared bus interface unit.    
     
     
       8. A data processing system as in  claim 7  wherein the digital signal execution unit includes an internal address generator for retrieving operands from either the shared internal memory array or the external memory system via the shared internal bus for use by the digital signal execution unit in executing the selected sequence of DSP instructions. 
     
     
       9. An integrated circuit data processing system for processing a digital signal, the data processing system comprising:
 (a) a digital signal execution unit that recovers digital data from the digital signal by executing a selected sequence of digital signal processor (DSP) instructions;    (b) a general purpose processor that selects the sequence of DSP instructions for execution by the digital signal execution unit from a set of DSP instructions and that performs general purpose processing tasks by executing general purpose instructions utilizing selected data;    (c) a shared internal bus for transferring both data and instructions and to which both the digital signal execution unit and the general purpose processor are connected; and    (d) a shared internal memory array connected to the shared internal bus via an internal input/output port of the shared internal memory array such that the shared internal memory array is accessible by the digital signal execution unit via the internal input/output port for transferring operands utilizable by the digital signal execution unit between the shared internal memory array and the digital signal execution unit on the shared internal bus and such that the shared internal memory array is accessible by the general purpose processor via the internal input/output port for transferring the general purpose instructions and the selected data between the shared internal memory array and the general purpose processor on the shared internal bus; wherein the digital signal execution unit includes an internal address generator for retrieving operands from the shared internal memory array via the shared internal bus for use by the digital signal execution unit in executing the selected sequence of DSP instructions.    
     
     
       10. An integrated circuit data processing system for processing a digital signal, the data processing system comprising:
 (a) a digital signal execution unit that recovers digital data from the digital signal by executing a selected sequence of digital signal processor (DSP) instructions;    (b) a general purpose processor that selects the sequence of DSP instructions for execution by the digital signal execution unit from a set of DSP instructions and that performs general purpose processing tasks by executing general purpose instructions utilizing selected data;    (c) a shared internal bus for transferring both data and instructions and to which both the digital signal execution unit and the general purpose processor are connected;    (d) a shared internal memory array connected to the shared internal bus via an internal input/output port of the shared internal memory array such that the shared internal memory array is accessible by the digital signal execution unit via the internal input/output port for transferring operands utilizable by the digital signal execution unit between the shared internal memory array and the digital signal execution unit on the shared internal bus and such that the shared internal memory array is accessible by the general purpose processor via the internal input/output port for transferring the general purpose instructions and the selected data between the shared internal memory array and the general purpose processor on the shared internal bus; wherein the DSP instructions and the general purpose instructions comprise subsets of a single instruction set executable by the data processing system; and    (e) an instruction sequencing unit connected to the shared internal bus for controlling the flow of execution of the DSP instructions and the general purpose instructions.    
     
     
       11. A data processing system for processing a digital signal, the data processing system comprising:
   a shared bus that transfers data and instructions;        a shared memory array that stores data and general purpose instructions and that is connected to transfer data and general purpose instructions between the shared bus and the shared memory array;        a digital signal execution unit  ( DSEU )  connected to the shared bus that processes the digital signal utilizing data transferred between the shared memory array and the DSEU on the shared bus and a selected sequence of individual DSEU instructions, the selected sequence of DSEU instructions including individual general purpose instructions transferred between the shared memory array and the DSEU on the shared bus; and        a general purpose processor  ( GPP )  connected to the shared bus for controlling the DSEU by selecting each general purpose instruction to be transferred to the DSEU from the shared memory array, the selected sequence of individual DSEU instructions executed by the DSEU being selectively configurable by the GPP selecting individual general purpose instructions.      
     
     
       12. The data processing system of  claim 11  wherein the DSEU has a register, and starts execution of a general purpose instruction in response to the GPP loading information into the register.  
     
     
       13. The data processing system of  claim 11  wherein the GPP loads data into a location, and the DSEU retrieves data required by the instruction from the location.  
     
     
       14. The data processing system of  claim 11  wherein the DSEU places the GPP in a continuous wait state while the DSEU executes the instruction.  
     
     
       15. The data processing system of  claim 11  wherein the GPP reads a status of the DSEU after the DSEU complete execution of the instruction.  
     
     
       16. The data processing system of  claim 11  wherein the GPP reads a value that results from executing the instruction after the DSEU completes execution of the instruction.  
     
     
       17. The data processing system of  claim 11  wherein the DSEU only executes a single general purpose instruction when said information is loaded into the register.