Fast cyclic redundancy check (CRC) generation

Abstract

A CRC generation unit is equipped with multiple polynomial division circuits (PDC) to perform multiple different bit lengths polynomial divisions in parallel, including outputting of multiple remainder values, for an iteration of an iterative CRC generation for a data block. In one embodiment, the unit also includes a selector to select one of the remainder values, and a register to store the selected remainder value, return the stored remainder value to the PDCs for formation of different bit length dividends, and output the stored remainder value of the last iteration as the generated CRC value. In one embodiment, the unit further includes alignment circuitry to align the data block. In one embodiment, multiple units are provided to generate the CRC values of successive variable length data blocks. In one embodiment, the units form a shared resource to multiple network traffic flow processing units of a network traffic routing IC.

1. An apparatus comprising:
 a plurality of polynomial division circuits to perform a plurality of different bit lengths polynomial divisions in parallel, including outputting a plurality of remainder values, for an iteration of an iterative CRC generation for a data block;  
 a selector coupled to the plurality of polynomial division circuits to select one of said remainder values outputted for the iteration of said iterative CRC generation; and  
 a register coupled to the selector and the polynomial division circuits to store the selected remainder value of the iteration, and to output the stored remainder value to the polynomial division circuits for use by the polynomial division circuits to form a plurality of different bit lengths dividends for the polynomial division circuits for a next iteration of the iterative CRC generation for the data block.  
 
     
     
       2. The apparatus of  claim 1 , wherein the data block is received through m groups of n-bit groups with the starting bit of the data block being located in one of the n-bits of the first n-bit group and the ending bit of the data block being located in one of n-bits of the last n-bit group, where m and n are integers greater than or equal to 1, and the apparatus further comprises an alignment unit coupled to polynomial division circuits to align the data block, such that the data block is provided to the polynomial division circuits through m groups of n-bit groups, but with the starting bit being located at the first bit of the first n-bit group. 
     
     
       3. The apparatus of  claim 2 , wherein n is an integer selected from a group of integers consisting of integers that are powers of 2. 
     
     
       4. The apparatus of  claim 1 , wherein each of the polynomial division circuits further includes an additional different plurality of input bit lines to receive a different number of input bits to be concatenated with the remainder value of an immediate prior iteration outputted from the register to form a dividend of different bit length for the next iteration of the iterative CRC generation for the data block. 
     
     
       5. The apparatus of  claim 1 , wherein the apparatus is disposed on an integrated circuit. 
     
     
       6. An apparatus comprising:
 a first plurality of polynomial division circuits to perform a first plurality of different bit lengths polynomial divisions in parallel, including outputting a first plurality of remainder values, for an iteration of a first iterative CRC generation for a first variable length data block;  
 a first selector coupled to the first plurality of polynomial division circuits to select one of said first remainder values outputted for the iteration of said first iterative CRC generation;  
 a first register coupled to the first selector and the first polynomial division circuits to store the selected remainder value of the iteration, and to output the stored remainder value to the first polynomial division circuits for use by the first polynomial division circuits to form a first plurality of different bit lengths dividends for the first polynomial division circuits for a next iteration of the first iterative CRC generation for the first variable length data block;  
 a second plurality of polynomial division circuits to perform a second plurality of different bit lengths polynomial divisions in parallel, including outputting a second plurality of remainder values, for an iteration of a second iterative CRC generation for a second variable length data block immediately following said first variable length data block;  
 a second selector coupled to the second plurality of polynomial division circuits to select one of said second remainder values outputted for the iteration of said second iterative CRC generation;  
 a second register coupled to the second selector and the second polynomial division circuits to store the selected remainder value of the iteration, and to output the stored remainder value to the second polynomial division circuits for use by the second polynomial division circuits to form a second plurality of different bit lengths dividends for the second polynomial division circuits for a next iteration of the second iterative CRC generation for the second variable length data block.  
 
     
     
       7. The apparatus of  claim 6 , wherein each of said first and second variable length data blocks is received through m groups of n-bit groups with the starting bit of the first/second variable length data block being located in one of the n-bits of the first n-bit group and the ending bit of the data block being located in one of n-bits of the last n-bit group, where m and n are integers greater than or equal to 1, and the apparatus further comprises a first and a second alignment unit correspondingly coupled to the first and second polynomial division circuits to align the first and the second variable length data block, such that each of the first/second variable length data block is provided to the first/second polynomial division circuits through m groups of n-bit groups, but with the starting bit being located at the first bit of the first n-bit group. 
     
     
       8. The apparatus of  claim 6 , wherein each of the first/second polynomial division circuits further includes an additional different plurality of input bit lines to receive a different number of input bits to be concatenated with the remainder value of an immediate prior iteration outputted from the first/second register to form a first/second dividend of different bit length for the next iteration of the first/second iterative CRC generation for the first/second variable length data block. 
     
     
       9. The apparatus of  claim 6 , wherein the apparatus is disposed on an integrated circuit. 
     
     
       10. An apparatus comprising:
 first alignment unit to align a first variable length data block received in first m groups of n-bit groups with the starting bit of the first variable length data block being located in one of the n-bits of the first n-bit group of the first m groups and the ending bit of the first variable length data block being located in one of n-bits of the last n-bit group of the first m groups, where m and n are integers greater than or equal to 1;  
 a first CRC generation unit coupled to the first alignment unit to iteratively generate a first CRC value for the first variable length data block, the first CRC generation unit including a first plurality of polynomial division circuits to perform a first plurality of polynomial divisions for a plurality of different length dividends in parallel for each iteration of the first iterative generation of the first CRC value of the first variable length data block;  
 second alignment unit to align a second variable length data block immediately following the first variable length data block, received in second m groups of n-bit groups with the starting bit of the second variable length data block being located in one of the n-bits of the first n-bit group of the second m groups and the ending bit of the second variable length data block being located in one of n-bits of the last n-bit group of the second m groups; and  
 a second CRC generation unit coupled to the second alignment unit to iteratively generate a second CRC value for the second variable length data block, the second CRC generation unit including a second plurality of polynomial division circuits to perform a second plurality of polynomial divisions for a plurality of different length dividends in parallel for each iteration of the second iterative generation of the first CRC value of the second variable length data block.  
 
     
     
       11. The apparatus of  claim 10 , wherein the first/second CRC generation unit further comprises:
 a first/second selector coupled to the first/second plurality of polynomial division circuits to select one of first/second plurality remainder values outputted for an iteration of the first/second iterative CRC generation; and  
 a first/second register coupled to the first/second selector and the first/second polynomial division circuits to store the selected remainder value of the iteration, and to output the stored remainder value to the first/second polynomial division circuits for use by the first/second polynomial division circuits to form a first/second plurality of different bit lengths dividends for the first/second polynomial division circuits for a next iteration of the first/second iterative CRC generation for the first/second variable length data block.  
 
     
     
       12. The apparatus of  claim 10 , wherein the apparatus is disposed on an integrated circuit. 
     
     
       13. A method comprising:
 aligning a first variable length data block received in first m groups of n-bit groups with the starting bit of the first variable length data block being located in one of the n-bits of the first n-bit group of the first m groups and the ending bit of the first variable length data block being located in one of n-bits of the last n-bit group of the first m-groups, where m and n are integers greater than or equal to 1;  
 iteratively generating a first CRC value for the first variable length data block, including for each iteration, performance of a first plurality of polynomial divisions for a plurality of different length dividends in parallel;  
 aligning a second variable length data block immediately following the first variable length data block, received in second m groups of n-bit groups with the starting bit of the second variable length data block being located in one of the n-bits of the first n-bit group of the second m groups and the ending bit of the second variable length data block being located in one of n-bits of the last n-bit group of the second m groups; and  
 iteratively generating a second CRC value for the second variable length data block, including for each iteration, performance of a second plurality of polynomial divisions for a plurality of different length dividends in parallel for each iteration of the second iterative generation of the first CRC value of the second variable length data block.  
 
     
     
       14. The method of  claim 13 , wherein each of the first/second iterative generation of the first/second CRC value for the first/second variable length data block comprises:
 selecting one of first/second plurality remainder values outputted for an iteration of the first/second iterative CRC generation; and  
 storing the selected remainder value of the iteration, and output the stored remainder value for use to form a first/second plurality of different bit lengths dividends for a next iteration of the first/second iterative CRC generation for the first/second variable length data block.  
 
     
     
       15. An apparatus comprising:
 a plurality of processing units to correspondingly process a plurality of network traffic flows; and  
 a shared CRC generation block coupled to the processing units to alternately generate a CRC value for a data block of a selected one of the network traffic flows, the shared CRC generation block including at least one CRC generation unit that iteratively generate a first CRC value for the data block of the selected one of the network traffic flows, the at least one CRC generation unit including a plurality of polynomial division circuits to perform a plurality of polynomial divisions for a plurality of different length dividends in parallel for each iteration of the iterative generation of the CRC value of the data block of the selected one of the network traffic flow.  
 
     
     
       16. The apparatus of  claim 15 , wherein the shared CRC generation block further comprises an alignment unit coupled to the plurality of polynomial division circuits of the at least one CRC generation unit to align the data block received in m groups of n-bit groups with the starting bit of the data block being located in one of the n-bits of the first n-bit group of the m groups and the ending bit of the data block being located in one of n-bits of the last n-bit group of the m groups, where m and n are integers greater than or equal to 1. 
     
     
       17. The apparatus of  claim 15 , wherein the shared CRC generation block further comprises:
 a selector coupled to the plurality of polynomial division circuits to select one of a plurality remainder values outputted for an iteration of the iterative CRC generation; and  
 a register coupled to the selector and the polynomial division circuits to store the selected remainder value of the iteration, and to output the stored remainder value to polynomial division circuits for use by the polynomial division circuits to form a plurality of different bit lengths dividends for the polynomial division circuits for a next iteration of the iterative CRC generation for the data block of the selected one of the network traffic flow.  
 
     
     
       18. The apparatus of  claim 15 , wherein the apparatus is disposed on an integrated circuit. 
     
     
       19. An apparatus comprising:
 a plurality of processing units to correspondingly process a plurality of network traffic flows; and  
 a shared CRC generation block coupled to the processing units to alternately generate CRC values for data blocks of a selected one of the network traffic flows, the shared CRC generation block including a first and a second CRC generation unit that iteratively generate a first and a second CRC value for a first and a second data block of the selected one of the network traffic flows, the first and second CRC generation units correspondingly including first and second plurality of polynomial division circuits to perform first and second plurality of polynomial divisions for first and second plurality of different length dividends in parallel for a first and a second iteration of a first and a second iterative generation of the first and the second CRC value of the first and second data block of the selected one of the network traffic flow.  
 
     
     
       20. The apparatus of  19 , wherein
 the first CRC generation unit includes a first alignment unit to align the first data block received in first m groups of n-bit groups with the starting bit of the first data block being located in one of the n-bits of the first n-bit group of the first m groups and the ending bit of the first data block being located in one of n-bits of the last n-bit group of the first m groups, where m and n are integers greater than or equal to 1; and  
 the second CRC generation unit includes a second alignment unit to align the second data block, which immediately follows the first data block, received in second m groups of n-bit groups with the starting bit of the second data block being located in one of the n-bits of the first n-bit group of the second m groups and the ending bit of the second data block being located in one of n-bits of the last n-bit group of the second m groups.  
 
     
     
       21. The apparatus of  claim 19 , wherein the first/second CRC generation unit further comprises:
 a first/second selector coupled to the first/second plurality of polynomial division circuits to select one of first/second plurality remainder values outputted for an iteration of the first/second iterative CRC generation; and  
 a first/second register coupled to the first/second selector and the first/second polynomial division circuits to store the selected remainder value of the iteration, and to output the stored remainder value to the first/second polynomial division circuits for use by the first/second polynomial division circuits to form a first/second plurality of different bit lengths dividends for the first/second polynomial division circuits for a next iteration of the first/second iterative CRC generation for the first/second data block of the selected one of the network traffic flows.  
 
     
     
       22. The apparatus of  claim 19  wherein the apparatus is disposed on an integrated circuit. 
     
     
       23. An apparatus comprising:
   a plurality of polynomial division circuits to perform a plurality of polynomial divisions in parallel to provide a plurality of remainder values for an iteration of an iterative CRC generation for a data block;        a selector coupled to the plurality of polynomial division circuits to select one of said remainder values for the iteration of said iterative CRC generation; and        a register coupled to the selector and the polynomial division circuits to store the selected remainder value of the iteration.     
     
     
       24. The apparatus of  claim 23 , wherein said data block comprises a variable length data block and said apparatus further comprises an alignment unit to align said variable length data block. 
     
     
       25. The apparatus of  claim 23 , wherein said polynomial division circuits are further adapted to form a plurality of dividends for the polynomial division circuits for a subsequent iteration of the iterative CRC generation for the data block based, at least in part, on said stored remainder value. 
     
     
       26. The apparatus of  claim 25 , wherein one or more of said polynomial division circuits comprises a plurality of input bit lines to receive input bits to be concatenated with said stored remainder value to form a dividend of a different bit length for said subsequent iteration. 
     
     
       27. An apparatus comprising:
   a first plurality of polynomial division circuits to perform a first plurality of polynomial divisions in parallel to provide a first plurality of remainder values for an iteration of a first iterative CRC generation for a first variable length data block;        a first selector coupled to the first plurality of polynomial division circuits to select one of said first remainder values for the iteration of said first Iterative CRC generation;        a first register coupled to the first selector and the first polynomial division circuits to store said selected first remainder value;        a second plurality of polynomial division circuits to perform a second plurality of polynomial divisions in parallel to provide a second plurality of remainder values for an iteration of a second iterative CRC generation for a second variable length data block immediately following said first variable length data block;        a second selector coupled to the second plurality of polynomial division circuits to select one of said second remainder values for the iteration of said second iterative CRC generation; and        a second register coupled to the second selector and the second polynomial division circuits to store said selected second remainder value.     
     
     
       28. The apparatus of  claim 27 , and further comprising:
   a first alignment unit to align said first variable length data block; and        a second alignment unit to align said second variable length data block.     
     
     
       29. The apparatus of  claim 27 , wherein said first polynomial division circuits are further adapted to form a plurality of dividends for the polynomial division circuits for a subsequent iteration of said first iterative CRC generation for the first variable length data block based, at least in part, on said stored first remainder value, and wherein said second polynomial division circuits are further adapted to form a plurality of dividends for the polynomial division circuits for a subsequent iteration of said second iterative CRC generation for the second variable length data block based, at least in part, on said stored second remainder value. 
     
     
       30. An apparatus comprising:
   a first alignment unit to align a first variable length data block;        a first CRC generation unit coupled to the first alignment unit, said first CRC generation unit including a first plurality of polynomial division circuits to perform a first plurality of polynomial divisions for a plurality of dividends in parallel for iterations of a first iterative generation of a first CRC value associated with the first variable length data block;        a second alignment unit to align a second variable length data block; and        a second CRC generation unit coupled to the second alignment unit, said second CRC generation unit including a second plurality of polynomial division circuits to perform a second plurality of polynomial divisions for a plurality of dividends in parallel for iterations of a second iterative generation of a second CRC value associated with the second variable length data block.     
     
     
       31. A method comprising:
   aligning a first variable length data block;        iteratively generating a first CRC value for said first aligned variable length data block, including performing a first plurality of polynomial divisions for a plurality of dividends in parallel in iterations of said generating a first CRC value;        aligning a second variable length data block, said second variable data block immediately following the first variable length data block; and        iteratively generating a second CRC value for said second aligned variable length data block, including performing a second plurality of polynomial divisions for a plurality of dividends in parallel in iterations of said generations of said second CRC value of the second variable length data block.     
     
     
       32. The method of  claim 31 , wherein said iteratively generating said first CRC and further comprises:
   selecting a remainder of at least one of said first plurality of polynomial divisions; and        storing said selected remainder of said first plurality of polynomial divisions.     
     
     
       33. The method of  claim 32 , and further comprising generating a subsequent iteration of said first CRC value based, at least in part, on said stored selected remainder of said first plurality of polynomial divisions. 
     
     
       34. The method of  claim 33 , wherein said generating a subsequent iteration of said first CRC value further comprises concatenating said stored selected remainder of said first plurality of polynomial divisions with input bits. 
     
     
       35. An apparatus comprising:
   a plurality of processing units to process an associated plurality of network traffic flows;        a shared CRC generation block including at least one CRC generation unit to iteratively generate a CRC value for a data block of an associated one of said network traffic flows, said at least one CRC generation unit comprising a plurality of polynomial division circuits to perform a plurality of polynomial divisions for a plurality of dividends in parallel for iterations of generation of said CRC value.     
     
     
       36. The apparatus of  claim 35 , and further comprising:
   a selector to select one of a plurality of remainder values resulting from an iteration of generation of said CRC value, and        wherein said CRC generation unit is further adapted to iteratively generate a subsequent iteration of said generation of said CRC value based, at least in part, on said selected one of a plurality of remainders.     
     
     
       37. The apparatus of  claim 35 , and further comprising an alignment unit to align said data block.