Method of and apparatus for providing look ahead column redundancy access within a memory

Abstract

A look ahead column redundancy circuit provides high speed memory access to both regular memory arrays and redundant memory arrays. In the preferred embodiment of the present invention, the information on both the address bus and the information on the next address bus are decoded by redundant column decoders in parallel. The decoded information from the redundant column decoders is then provided to a redundancy column pathway as the addressing information from the address bus and the next address bus is provided to a main column pathway. The information on the address bus is latched when beginning at a new column address. The information on the next address bus is latched for the next column address when operating in a burst cycle mode. The main column pathway preferably includes a latch, a main column decoder and a main column select circuit. A disable signal is also activated by the redundant column decoders if the addressing information for a current memory access operation corresponds to an address within the redundant memory array. When activated, the disable signal disables the main column select circuit within the main column pathway. If the addressing information for a current memory access operation does not correspond to an address within the redundant memory array, then the memory access operation is performed within the main memory array without any delays. Since the decoding is performed before the information is latched onto the column address bus, the proper pathway is selected without the need for any additional delay.

1. An apparatus for accessing a memory structure including a main memory array and a redundant memory array comprising:
 a. an address bus for carrying addressing information for a current memory access operation;  
 b. a main column pathway including a main column decoder for decoding addressing information and a main select circuit for selecting appropriate groups of memory cells within the main memory array for the current memory access operation; and  
 c. a redundant column pathway including a redundant column decoder for decoding addressing information having a first output for providing a decoded redundant address and a second output for providing a disable signal, and further including a redundant select circuit for selecting appropriate groups of memory cells within the redundant memory array for the current memory access operation if the first output of the redundant column decoder is providing the decoded redundant address and the second output is providing the disable signal, wherein the addressing information is decoded by the redundant column decoder before the addressing information is decoded by the main column decoder.  
 
     
     
       2. The apparatus as claimed in  claim 1  wherein the second output of the redundant column decoder provides the disable signal to the main select circuit if the current memory access operation is accessing memory cells within the redundant memory array. 
     
     
       3. The apparatus as claimed in  claim 1  wherein the redundant column decoder is provided the addressing information before the main column pathway. 
     
     
       4. The apparatus as claimed in  claim 3  wherein the main column pathway is provided the addressing information and the redundant select circuit is provided the decoded redundant address from the redundant column decoder in response to a control signal. 
     
     
       5. The apparatus as claimed in  claim 4  wherein the groups of memory cells are columns. 
     
     
       6. A method of completing memory access operations within a memory structure including a main memory array and a redundant memory array, comprising the steps of:
 a. determining from addressing information for a current memory access operation if the addressing information represents an address included within the redundant memory array;  
 b. providing the addressing information for the current memory access operation to a main column pathway after the step of determining is completed;  
 c. decoding a main address within the main memory array corresponding to the addressing information;  
 d. activating a group of main memory cells within the main memory array corresponding to the main address; and  
 e. providing a disable signal to a main column select circuit and a decoded redundant address to a redundant column pathway if the addressing information represents an address included within the redundant memory array and selecting the redundant column pathway.  
 
     
     
       7. The method as claimed in  claim 6  further comprising the step of disabling the step of activating a group of main memory cells, if the addressing information represents an address included within the redundant memory array. 
     
     
       8. The method as claimed in  claim 6  further comprising the step of activating a group of redundant memory cells within the redundant memory array, if the addressing information represents an address included within the redundant memory array. 
     
     
       9. The method as claimed in  claim 8  wherein the step of providing the disable signal is completed before the step of providing the addressing information. 
     
     
       10. The method as claimed in  claim 6  wherein the groups of main memory cells are columns within the main memory array. 
     
     
       11. The method as claimed in  claim 8  wherein the groups of redundant memory cells are columns within the redundant memory array. 
     
     
       12. An apparatus for controlling access to a memory structure including a regular memory array and a redundancy memory array comprising:
 a. an address bus for carrying addressing information for a current memory access operation;  
 b. a first redundancy column decoder coupled to the address bus for decoding the addressing information, the first redundancy column decoder including a first output for providing a first decoded redundancy address and a second output for providing a disable signal;  
 c. a first pass through circuit coupled to the address bus for passing through the addressing information in response to a first control signal;  
 d. a first latching circuit coupled to the first pass through circuit for latching the addressing information which has passed through the first pass through circuit;  
 e. a regular column decoder circuit coupled to the first latching circuit for decoding the addressing information and providing a decoded regular address;  
 f. a second pass through circuit coupled to the first output of the first redundancy column decoder for passing through the first decoded redundancy address in response to the first control signal;  
 g. a second latching circuit coupled to the second pass through circuit for latching the first decoded redundancy address from the first output of the first redundancy column decoder which has passed through the second pass through circuit;  
 h. a regular column select circuit coupled to the regular column decoder to receive the decoded regular address and to select a corresponding regular column address within the regular memory array, wherein the regular column select circuit is also coupled to receive the disable signal from the second output of the first redundancy column decoder for disabling the regular column select circuit if the addressing information corresponds to an address within the redundancy memory array; and  
 i. a redundancy column select circuit coupled to the second latching circuit to receive the first decoded redundancy address and to select a corresponding redundant column address within the redundancy memory array, if the addressing information corresponds to an address within the redundancy memory array.  
 
     
     
       13. The apparatus as claimed in  claim 12  wherein the first redundancy column decoder is provided the addressing information before the first latching circuit. 
     
     
       14. The apparatus as claimed in  claim 13  wherein the first control signal is a column address enable signal. 
     
     
       15. The apparatus as claimed in  claim 12  further comprising:
 a. a next address bus for carrying next addressing information for a next memory access operation;  
 b. a second redundancy column decoder coupled to the next address bus for decoding the next addressing information, the second redundancy column decoder including a third output for providing a second decoded redundancy address and a fourth output for providing the disable signal;  
 c. a third pass through circuit coupled to the next address bus for passing through the next addressing information in response to a second control signal, wherein the third pass through circuit is also coupled to pass the next addressing information through to the first latching circuit; and  
 d. a fourth pass through circuit coupled to the third output of the second redundancy column decoder for passing through the second decoded redundancy address in response to the second control signal, wherein the fourth pass through circuit is also coupled to pass the second decoded redundancy address through to the second latching circuit.  
 
     
     
       16. The apparatus as claimed in  claim 15  wherein the first and second column decoders are provided the addressing information and the next addressing information before the first latching circuit. 
     
     
       17. The apparatus as claimed in  claim 16  wherein the second control signal is a column address counter signal. 
     
     
       18. A memory subsystem comprising:
   an address bus;        a main column pathway configured to receive an address from the address bus and further configured to be coupled to a main memory array, wherein the main column pathway includes at least a first storage element and a first decoder; and        a redundant column pathway configured to receive the address from the address bus and further configured to be coupled to a redundant memory array, wherein the redundant column pathway includes at least a second storage element and a second decoder;        wherein in the main column pathway, the first storage element is configured to store the address prior to the address being decoded by the first decoder, and in the redundant column pathway, the second decoder is configured to decode the address prior to an output of the second decoder being stored within the second storage element.     
     
     
       19. The memory subsystem as recited in  claim 18 , wherein the second decoder is configured to assert a disable signal if a current memory access operation is accessing memory cells within the redundant memory array, and wherein the main column pathway further includes a first select circuit coupled to receive the disable signal, wherein the first select circuit is configured to be disabled responsive to receiving the disable signal. 
     
     
       20. The memory subsystem as recited in  claim 19 , wherein the first select circuit is coupled to receive an output from the first decoder, and wherein the redundant column pathway further includes a second select circuit coupled to receive an output from the second storage element. 
     
     
       21. The memory subsystem as recited in  claim 20 , wherein the first select circuit is coupled to provide access to the main memory array, and wherein the second select circuit is coupled to provide access to the redundant memory array. 
     
     
       22. The memory subsystem as recited in  claim 19 , wherein the second decoder is configured to not assert the disable signal if the current memory access operation is accessing memory cells within the main memory array. 
     
     
       23. The memory subsystem as recited in  claim 19 , wherein the memory subsystem further comprises a next address bus coupled to provide the address to the first storage element and further coupled to provide address signals to a third decoder, wherein the third decoder is in the redundant column pathway, and wherein the next address bus is configured to convey the address during a burst cycle mode. 
     
     
       24. The memory subsystem as recited in  claim 23 , wherein the third decoder is configured to assert the disable signal if the address received from the next address bus indicates that the current memory access operation is accessing cells in the redundant memory array. 
     
     
       25. The memory subsystem as recited in  claim 18 , wherein each of the first and second storage elements is a latch. 
     
     
       26. A system comprising:
   a main memory array;        a redundant memory array;        an address bus;        a first storage element;        a main memory decoder configured to decode an address stored in the first storage element;        a redundant memory decoder configured to decode an address sent on the address bus and configured to generate an indication of whether the sent address is associated with any memory cells in the redundant memory array;        a second storage element coupled to store an output of the redundant memory decoder; and        selection circuitry configured to selectively cause either the main memory array or the redundant memory array to be accessed depending on the indication.     
     
     
       27. The system as recited in  claim 26 , wherein the selection circuitry includes a main memory select circuit coupled to provide access to the main memory array and a redundant memory select circuit coupled to provide access to the redundant memory array, wherein the main memory select circuit is coupled to receive the indication. 
     
     
       28. The system as recited in  claim 27 , wherein the main memory select circuit is coupled to receive an output from the main memory decoder, and wherein the redundant memory select circuit is coupled to receive an output from the second storage element. 
     
     
       29. The system as recited in  claim 27 , wherein the main memory select circuit is configured to be disabled responsive to receiving the indication. 
     
     
       30. The system as recited in  claim 27 , wherein the redundant memory decoder is configured to not assert the indication if the address is associated with memory cells in the main memory array. 
     
     
       31. The system as recited in  claim 27  further comprising:
   a next address bus configured to convey a next address, wherein the first storage element is configured to store the address conveyed on the next address bus; and        a next address decoder configured to decode the next address conveyed on the next address bus and configured to generate an indication if the next address is associated with memory cells in the redundant memory array;        wherein the selection circuitry configured to selectively cause either the main memory array or the redundant memory array to be accessed depending on a state of the indication.     
     
     
       32. The system as recited in  claim 31 , wherein the main memory select circuit is coupled to receive the indication from the next address decoder, and wherein the main memory select circuit is configured to be disabled responsive to receiving the indication. 
     
     
       33. The system as recited in  claim 31 , wherein the next address decoder is configured to not assert the indication if the next address is associated with memory cells in the main memory array. 
     
     
       34. The system as recited in  claim 31 , wherein the second storage element is configured to store an output of the next address decoder. 
     
     
       35. The system as recited in  claim 31 , wherein the next address is associated with a burst cycle mode. 
     
     
       36. The system as recited in  claim 26 , wherein each of the first and second storage elements is a latch. 
     
     
       37. An apparatus configured to receive addressing information corresponding to a memory access, comprising:
   a main memory control pathway configured to receive said addressing information, wherein said main memory control pathway includes a main decoder configured to decode said addressing information, producing decoded addressing information usable to select a group of memory locations in a main memory array;        a redundant memory control pathway configured to receive said addressing information, wherein said redundant memory control pathway includes a redundant decoder;        wherein, if said addressing information corresponds to a group of memory locations in a redundant memory array, said redundant decoder is configured to provide via a first output, decoded addressing information usable to select said group of memory locations in said redundant memory array, and, via a second output, an activated disable signal;        wherein said redundant decoder is configured to decode said addressing information before said main decoder.     
     
     
       38. The apparatus of  claim 37 , wherein said main memory control pathway and said redundant memory control pathway and configured to select columns in said main memory array and redundant memory array respectively. 
     
     
       39. The apparatus of  claim 37 , wherein said redundant decoder is configured to provide said activated disable signal to said main memory control pathway, disabling said main memory control pathway from selecting said group of memory locations in said main memory array. 
     
     
       40. The apparatus of  claim 37 , wherein addressing information is provided to said redundant decoder before being provided to said main memory control pathway. 
     
     
       41. The apparatus of  claim 37 , wherein the apparatus is an electronics system including random access memory. 
     
     
       42. The apparatus of  claim 37 , wherein the apparatus is configured to operate in burst mode. 
     
     
       43. The apparatus of  claim 37 , wherein, if said addressing information does not correspond to a group of memory locations in said redundant memory array, said main memory control pathway is configured to select a group of memory locations in said main memory array. 
     
     
       44. An apparatus, comprising:
   a first memory control unit configured to receive a memory address, generate first control information usable to select a group of locations within a main memory array, and convey said first control information to said main memory array;        a second memory control unit configured to receive said memory address;        wherein, if said memory address corresponds to a group of locations in a redundant memory array, said second memory control unit is configured to:      generate second control information usable to select said group of locations within said redundant memory array; and        disable said first memory control unit from conveying said first control information to said main memory array.       
     
     
       45. The apparatus of  claim 44 , wherein the apparatus is an electronics system including random access memory. 
     
     
       46. The apparatus of  claim 44 , wherein first control information is usable to select one or more columns with said main memory array, and wherein said second control information is usable to select one or more columns within said redundant memory array. 
     
     
       47. The apparatus of  claim 44 , wherein said apparatus is configured to operate in burst mode. 
     
     
       48. The apparatus of  claim 44 , wherein if said memory address does not correspond to a group of locations in said redundant memory array, said first memory control unit is configured to select said group of locations within said main memory array specified by said conveyed first control information. 
     
     
       49. An apparatus, comprising:
   a main address pathway configured to receive a memory address, generate first address selection information, and convey said first address selection information to a main memory array,        a redundant address pathway configured to receive said memory address, wherein said redundant address pathway, in response to determining that a group of locations corresponding to said memory address is stored in a redundant memory array, is configured to:      generate second address selection information and convey said second address selection information to said redundant memory array; and        send an indication to said main address pathway that a group of locations corresponding to said memory address is stored in said redundant memory array;          wherein said indication is received by said main address pathway before said main address pathway conveys said first address selection information to said main memory array.     
     
     
       50. The apparatus of  claim 49 , wherein said apparatus is an electronics system including random access memory. 
     
     
       51. The apparatus of  claim 49 , wherein said apparatus is configured to operate in burst mode. 
     
     
       52. The apparatus of  claim 49 , wherein said indication is an activated disable signal, and wherein said main address pathway is configured such that receiving said activated disable signal prevents said main address pathway from conveying said first address selection information to said main memory array. 
     
     
       53. An apparatus, comprising:
   first means for receiving a memory address and generating, in response thereto, information usable to select a group of memory cells in a first memory array;        second means for receiving said memory address; for determining whether said memory address corresponds to one or more locations in a second memory array; and, if so,      for generating information usable to select a group of memory cells in said second memory array and activating a disable signal;          wherein said second means is configured to determine whether said memory address corresponds to said one or more locations in said second memory array before said first means generates said information usable to select said group of memory cells in said first memory array.     
     
     
       54. The apparatus of  claim 53 , wherein said apparatus is an electronics system including random access memory. 
     
     
       55. The apparatus of  claim 53 , wherein said first means, in response to receiving said activated disable signal, is configured to disable selection of said group of memory cells in said first memory array. 
     
     
       56. A method, comprising:
   determining, in a redundant memory control pathway, whether addressing information for a current memory access corresponds to one or more locations within a redundant memory array;        after said determining:      providing said addressing information to a main memory control pathway; and        decoding said addressing information provided to said main memory control pathway; and          if said addressing information corresponds to one or more locations within said redundant memory array:      providing a disable signal to said main memory control pathway; and        selecting said one or more locations within said redundant memory array corresponding to said addressing information.       
     
     
       57. The method of  claim 56 , further comprising said main memory control pathway operating in burst mode. 
     
     
       58. A method, comprising:
   decoding a memory address in a first memory control unit;        determining, in a second memory control unit, whether said memory address corresponds to one or more locations in a redundant memory array, and, if so:      generating address control information usable to select said one or more locations in said redundant memory array; and        providing a disable signal to said first memory control unit;          wherein said determining by said second memory control unit is performed before said decoding by said first memory control unit.     
     
     
       59. The method of  claim 58 , wherein said determining is performed by decoding said memory address within said second memory control unit. 
     
     
       60. The method of  claim 58 , wherein said providing said disable signal to said first memory control unit disables said first memory control unit from selecting one or more locations in a main memory array. 
     
     
       61. The method of  claim 58 , further comprising said first memory control unit operating in burst mode. 
     
     
       62. The method of  claim 61 , further comprising said second memory control unit operating in burst mode. 
     
     
       63. A method, comprising:
   providing a memory address to a first memory control unit and a second memory control unit corresponding to a first memory array and a second memory array, respectively;        determining, in said second memory control unit, whether said memory address corresponds to one or more locations in said second memory array, and, if so:      generating address control information usable to select said one or more locations within said second memory array; and        providing a disable signal to a first memory control unit prior to said first memory control unit generating address control information usable to select one or more locations within said first memory array.       
     
     
       64. A method of completing memory access operations within a memory structure including a main memory array and a redundant memory array, comprising:
   determining from addressing information for a current memory access operation if the addressing information represents an address included within the redundant memory array;        providing the addressing information for the current memory access operation to a main column pathway after the step of determining is completed;        decoding a main address within said main memory array corresponding to the addressing information;        if the addressing information represents an address included within the redundant memory array:      providing a disable signal to a main column select circuit and providing a decoded redundant address to a redundant column pathway; and        selecting the redundant column pathway.       
     
     
       65. The method of  claim 64 , further comprising activating a group of cells in said main memory array if said addressing information does not represent an address included within the redundant array.