Circuit layout arrangement for key switch signal recognition

Abstract

A key switch signal recognition circuit including a plurality of key switch buttons, a plurality of key switch signal output lines, and a plurality of key switch button contact areas is disclosed. Each of the key switch contact areas includes a first wire set and a second wire set. The first wire set has at least one wire, and each wire of the first wire set has one end connected to a common line and an opposite end forming an open end. The second wire set has at least one wire respectively disposed in parallel to and electrically insulated from the wire of the first wire set. The wire of the second wire set is respectively connected to a key switch signal output line. When depressing one key switch button to touch the corresponding key switch button contact area, the electrically conductive element of the depressed key switch button electrically connects the first wire set and second wire set of the touched key switch contact area, causing the respective key switch signal output line to send a key switch signal corresponding to the depressed key switch button.

1. A key switch signal recognition circuit comprising:
 a plurality of key switch buttons, said key switch buttons each provided with an electrically conductive element;  
 a plurality of key switch key signal output lines;  
 an AND gate having an output and a plurality of inputs respectively connected to said plurality of key switch key signal output lines; and  
 a plurality of contact areas arranged on a substrate corresponding to said key switch buttons, said contact areas each comprising a first wire set and a second wire set, said first wire set comprising at least one wire having one end connected to a common line and an opposite end forming an open end, said second wire set comprising at least one wire respectively disposed in parallel to and electrically insulated from the wire of said first wire set, the wire of said second wire set being respectively connected to the key switch signal output line which is selected subject to a predetermined bit encoding mode;  
 when one of said key switch buttons is depressed to touch the corresponding contact area, the electrically conductive element of the depressed key switch button electrically connects the first wire set and second wire set of the touched contact area, causing the respective key switch signal output line to send a key switch signal corresponding to the depressed key switch button, said output of said And  AND gate outputting a triggering signal responsive to the key switch signal output line of a corresponding contact area is at a logically high level.  
 
     
     
       2. The key switch signal recognition circuit of  claim 1 , wherein said bit encoding mode is a BCD encoding format. 
     
     
       3. The key switch signal recognition circuit of  claim 1 , wherein said key switch signal output lines comprises a grounding wire. 
     
     
       4. The key switch signal recognition circuit of  claim 1 , wherein the open end of the wire of the first wire set and the second wire set is terminated into two parallel end portions. 
     
     
       5. The key switch signal recognition circuit of  claim 1 , wherein the key switch signal output lines are further respectively connected to a debouncing circuit. 
     
     
       6. An apparatus comprising:
   two or more key switch buttons;        two or more key switch signal output lines;        an AND gate having an output and a plurality of inputs respectively connected to said two or more key switch signal output lines; and        two or more contact areas corresponding to said two or more key switch buttons, said contact areas connected to at least one of said two or more key switch signal output lines, and configured to cause at least one of said two or more key switch signal output lines to send a key switch signal in response to a depressed corresponding key switch button, wherein at least one of said two or more contact areas is connected to only one of said two or more output lines, wherein at least one of said two or more contact areas is connected to two or more of said two or more output lines, and        wherein said AND gate is configured to output a triggering signal if the key switch signal output line of a corresponding contact area is at a logically high level.      
     
     
       7. The apparatus of  claim 6 , wherein said two or more key switch buttons are greater in number than said two or more key switch signal output lines.  
     
     
       8. The apparatus of  claim 6 , wherein said two or more key switch buttons comprise an electrically conductive element, said electrically conductive element configured to electrically connect a first wire set and a second wire set of at least one of said two or more contact areas if one of said two or more key switch buttons is depressed, said first wire set comprising at least one wire having one end connected to a common line and an opposite end forming an open end, and said second wire set connected to at least one of said two or more key switch signal output lines. 
     
     
       9. The apparatus of  claim 8 , wherein said first wire set and said second wire set of said at least one of said two or more contact areas are connected to said two or more key switch signal output lines according to a predetermined bit encoding mode.  
     
     
       10. The apparatus of  claim 9 , wherein said bit encoding mode comprises a BCD encoding format.  
     
     
       11. The apparatus of  claim 6 , wherein said two or more key switch signal output lines comprise a grounding wire.  
     
     
       12. The apparatus of  claim 6 , wherein said two or more contact areas are arranged on a substrate, said two or more contact areas comprising a first wire set and a second wire set, said first wire set comprising at least one wire having one end connected to a common line and an opposite end forming an open end, said second wire set comprising at least one wire respectively disposed in parallel to and electrically insulated from the wire of said first wire set, the wire of said second wire set being respectively connected to at least one of said two or more key switch signal output lines. 
     
     
       13. The apparatus of  claim 12 , wherein the open end of the wire of the first wire set and the second wire set is terminated into two parallel end portions.  
     
     
       14. The apparatus of  claim 6 , wherein said two or more key switch signal output lines are connected to a debouncing circuit. 
     
     
       15. A method comprising:
   causing at least one of two or more key switch signal output lines to send a key switch signal in response to a depressed corresponding key switch button, wherein at least one of two or more contact areas corresponding to said two or more key switch buttons is connected to only one of said two or more key switch signal output lines, and wherein at least one of said two or more contact areas is connected to two or more key switch signal output lines;        receiving said key switch signal via at least one of two or more inputs of an AND gate connected to said two or more key switch signal output lines; and        outputting a triggering signal at least via an output of said AND gate if the key switch signal output line is at a logically high level.      
     
     
       16. The method of  claim 15 , wherein said key switch signal is sent at least via said two or more key switch signal output lines, and wherein said two or more key switch buttons are greater in number than said two or more key switch signal output lines.  
     
     
       17. A method of  claim 15 , further comprising processing said key switch signal of said two or more key switch signal output lines at least via a bit encoding mode.  
     
     
       18. The method of  claim 17 , wherein said bit encoding mode comprises a BCD encoding format. 
     
     
       19. The method of  claim 15 , further comprising touching a contact area corresponding to at least one of said two or more key switch buttons if at least one of said two or more key switch buttons is depressed to cause at least one of two or more key switch signal output lines to send said key switch signal.  
     
     
       20. The method of  claim 15 , further comprising processing said key switch signal of said two or more key switch signal output lines at least via a debouncing circuit.  
     
     
       21. The key switch signal recognition circuit of  claim 1 , wherein at least one of said plurality of contact areas is connected to the key switch signal output line by only one wire of said second wire set, and wherein at least one of said plurality of contact areas is connected to the key switch signal output line by two or more wires of said second wire set.  
     
     
       22. An apparatus comprising:
   key switch signal output line means for sending a key switch signal;        key switch button means for switching said key switch signal output line means;        an AND gate means having an output and a plurality of inputs respectively for connecting to said key switch signal output line means; and        contact area means corresponding to said key switch button means, said contact area means connected to at least one of said key switch signal output line means, and said contact area means configured to cause at least one of said key switch signal output line means to send a key switch signal in response to a depressed corresponding key switch button means, wherein at least one of said contact area means is connected to only one of said key switch signal output line means, wherein at least one of said contact area means is connected to two or more of said key switch signal output line means, and        wherein said AND gate means is further configured to output a triggering signal if the key switch signal output line means of a corresponding contact area means is at a logically high level.     
     
     
       23. The apparatus of  claim 22 , further comprising means for processing said key switch signal of said two or more key switch signal output lines at least via a bit encoding mode. 
     
     
       24. The apparatus of  claim 23 , wherein said bit encoding mode comprises a BCD encoding format. 
     
     
       25. The apparatus of  claim 22 , further comprising means for processing said key switch signal of said key switch signal output line means to prevent the respective key switch signal output line means to output an unstable signal.