Impedance blocking filter circuit

Abstract

An impedance blocking filter circuit is provided for use in telecommunication systems for interconnecting between incoming telephone lines and customer's terminal equipment so as to unconditionally block impedances above 20 KHz a desired frequency range due to the customer's terminal equipment from an ADSL a DSL network unit and/or home networking interface unit. The filter circuit includes first, second, and third inductors connected in series between a first input terminal and a first common point. A first resistor has its one end connected also to the first common point and its other end connected to a first output terminal. Fourth, fifth and sixth inductors are connected in series between a second input terminal and a second common point. A second resistor has its one end also connected to the second common point and its other end connected to a second output terminal. A capacitor has its ends connected across the first and second common points. In another aspect, the filter circuit also includes current limiting protection circuitry for reducing ring trip, dial pulse and off-hook transient current spikes. In one exemplary embodiment, the filter circuit is adapted to block impedances above 20 KHz, and comprises a series of inductors disposed electrically between respective ones of first and second input terminals and output terminals. At least one capacitor and first and second resistors are also present in the circuit.

1. An impedance blocking filter circuit used in telecommunication systems for interconnecting between incoming telephone lines and customer's terminal equipment so as to unconditionally block impedances from above 20 KHz due to the customer's terminal equipment from an ADSL network unit and/or home networking interface unit, said filter circuit comprising:
 first, second, and third inductors connected in series between a first input terminal and a first common point;    said first inductor having its one end connected to said first input terminal and its other end connected to one end of said second inductor, said second inductor having its other end connected to one end of said third inductor, said third inductor having its other end connected to said first common point;    a first resistor having its one end also connected to said first common point and its other end connected to a first output terminal;    fourth, fifth, and sixth inductors connected in series between a second input terminal and a second common point;    said four inductor having its one end connected to said second input terminal and its other end connected to one end of said fifth inductor, said fifth inductor having its other end connected to one end of said sixth inductor, said sixth inductor having its other end connected to said second common point;    a second resistor having its one end also connected to said second common point and its other end connected to a second output terminal; and    a capacitor having its one end connected to said first common point and its other end connected to said second common point.    
     
     
       2. An impedance blocking filter circuit as claimed in  claim 1 , wherein said first and fourth inductors are comprised of ferrite toroids. 
     
     
       3. An impedance blocking filter circuit as claimed in  claim 2 , wherein said second and fifth inductors have values on the order of 220 μH. 
     
     
       4. An impedance blocking filter circuit as claimed in  claim 3 , wherein said third and sixth inductors have values on the order of 10 mH. 
     
     
       5. An impedance blocking filter circuit as claimed in  claim 4 , wherein said first and second resistors have values on the order of 22 Ohms. 
     
     
       6. An impedance blocking filter circuit as claimed in  claim 5 , wherein said capacitor has the value on the order of 22 nf. 
     
     
       7. An impedance blocking filter circuit as claimed in  claim 1 , further comprising current limiting protection means connected between said common points and said output terminals for reducing current spikes caused by the customer's terminal equipment going off-hook. 
     
     
       8. An impedance blocking filter circuit as claimed in  claim 7 , wherein said current limiting protection means as comprised of first and second depletion mode field-effect transistors and first and second transient protection varistors. 
     
     
       9. An impedance blocking filter circuit as claimed in  claim 8 , wherein said first depletion mode field-effect transistor has its conduction path electrodes interconnected between said first common point and said one end of said first resistor and its gate electrode connected to said other end of said first resistor, said second depletion mode field-effect transistor having its conduction path electrodes interconnected between said second common point and said one end of said second resistor and its gate electrode connected to said other end of said second resistor, said first varistor having its one end connected also to said first common point and its other end connected to said first output terminal, said second varistor having its one end connected also to said second common point and its other end connected to said second output terminal. 
     
     
       10. An impedance blocking filter circuit used in telecommunication systems for interconnecting between incoming telephone lines and customer's terminal equipment so as to unconditionally block impedances from above 20 KHz due to the customer's terminal equipment from an ADSL network unit and/or home networking interface unit, said filter circuit comprising:
 first, second, and third inductors connected in series between a first input terminal and a first common point;    said first inductor having its one end connected to said first input terminal and its other end connected to one end of said second inductor, said second inductor having its other end connected to one end of said third inductor, said third inductor having its other end connected to said first common point;    a seventh inductor and a first resistor connected in series between said first common point and a first output terminal, said seventh inductor having its one end connected also to said first common point and its other end connected to one end of said first resistor, said first resistor having its other end connected to a first output terminal;    fourth, fifth, and sixth inductors connected in series between a second input terminal and a second common point;    said four inductor having its one end connected to said second input terminal and its other end connected to one end of said fifth inductor, said fifth inductor having its other end connected to one end of said sixth inductor, said sixth inductor having its other end connected to said second common point;    an eighth inductor and a second resistor connected in series between said second common point and a second output terminal, said eighth inductor having its one end connected also to said second common point and its other end connected to one end of said second resistor, said second resistor having its other end connected to a second output terminal; and    a capacitor having its one end connected to said first common point and its other end connected to said second common point.    
     
     
       11. An impedance blocking filter circuit as claimed in  claim 10 , wherein said first and fourth inductors are comprised of ferrite toroids. 
     
     
       12. An impedance blocking filter circuit as claimed in  claim 11 , wherein said second and fifth inductors have values on the order of 220 μH. 
     
     
       13. An impedance blocking filter circuit as claimed in  claim 12 , wherein said third and sixth inductors have values on the order of 5-10 mH. 
     
     
       14. An impedance blocking filter circuit as claimed in  claim 13 , wherein said seventh and eighth inductors have values on the order of 5-10 mH. 
     
     
       15. An impedance blocking filter circuit as claimed in  claim 14 , wherein said first and second resistors have values on the order of 22 Ohms. 
     
     
       16. An impedance blocking filter circuit as claimed in  claim 15 , wherein said capacitor has the value on the order of 47 nf. 
     
     
       17. An impedance blocking filter circuit as claimed in  claim 1 , further comprising home network demarcation filter means interconnected between the incoming telephone lines and internal house wiring for blocking the impedance of the customer's terminal equipment from home networking signals. 
     
     
       18. An impedance blocking filter circuit as claimed in  claim 17 , said demarcation filter means is comprised of six inductors and two capacitors. 
     
     
       19. An impedance blocking filter circuit as claimed in  claim 10 , further comprising home network demarcation filter means interconnected between the incoming telephone lines and internal house wiring for blocking the impedance of the customer's terminal equipment from home networking signals. 
     
     
       20. An impedance blocking filter circuit as claimed in  claim 19 , said demarcation filter means is comprised of six inductors and two capacitors. 
     
     
       21. A telecommunications filter circuit having high- frequency impedance blocking capabilities, comprising:      at least three first inductors electrically disposed between a first line side input terminal and a first common point;        at least three second inductors electrically disposed between a second line side input terminal and a second common point;        at least one capacitor disposed electrically between said first and second common points;        at least one first resistor disposed electrically between said first common point and a first output terminal; and        at least one second resistor disposed electrically between said second common point and a second output terminal.     
     
     
       22. The filter circuit of  claim 21 , further comprising:
   at least one third inductor disposed electrically between said first common point and said at least one first resistor; and        at least one fourth inductor disposed electrically between said second common point and said at least one second resistor.     
     
     
       23. The filter circuit of  claim 21 , wherein said high- frequency impedance blocking capability comprises the capability to block impedances above approximately  20  kHz.   
     
     
       24. The filter circuit of  claim 21 , wherein at least one of each of said three first inductors and said three second inductors comprises a ferrite toroid. 
     
     
       25. The filter circuit of  claim 24 , wherein at least one of each of said three first and second inductors has an inductance value on the order of  220  μH. 
     
     
       26. The filter circuit of  claim 25 , wherein at least one of each of said three first and second inductors has an inductance value on the order of  10  mH. 
     
     
       27. The filter circuit of  claim 21 , wherein at least one first and second resistors each have a resistance value on the order of  22  Ohms. 
     
     
       28. The filter circuit of  claim 22 , wherein at least one of each of said three first and second inductors comprises a ferrite toroid. 
     
     
       29. The filter circuit of  claim 28 , wherein at least one of each of said three first and second inductors has an inductance value on the order of  220  μH. 
     
     
       30. The filter circuit of  claim 29 , wherein at least one of each of said three first and second inductors has an inductance value on the order of  5  mH. 
     
     
       31. The filter circuit of  claim 30 , wherein at least one third and fourth inductors each has an inductance value on the order of  5  mH. 
     
     
       32. The filter circuit of  claim 22 , wherein at least one first and second resistors each have a resistance value on the order of  22  Ohms. 
     
     
       33. The filter circuit of  claim 21 , wherein said at least one capacitor has a capacitance value on the order of  22  nf. 
     
     
       34. The filter circuit of  claim 21 , wherein said circuit is adapted for interconnection between incoming telephone lines and a customer's terminal equipment and configured so as to unconditionally block impedances from above  20  KHz associated with the customer's terminal equipment from an ADSL network unit and/or home networking interface unit. 
     
     
       35. A telecommunications filter circuit comprising:
   at least one first inductor electrically disposed between a first input terminal and a first common point;        at least one second inductor electrically disposed between a second input terminal and a second common point;        at least one capacitor disposed electrically between said first and second common points; and        a substantially transistorized current limiter disposed electrically between said first and second common points and first and second equipment side output terminals.     
     
     
       36. The filter circuit of  claim 35 , wherein said current limiter is adapted to reduce current spikes caused by terminal equipment coupled to said output terminals going off- hook.   
     
     
       37. The filter circuit of  claim 35 , wherein said current limiter comprises first and second field- effect transistors and first and second varistors.   
     
     
       38. The filter circuit of  claim 37 , wherein said current limiter further comprises first and second resistors, said first field- effect transistor having its conduction path electrodes interconnected between said first common point and a first end of said first resistor and its gate electrode connected to a second end of said first resistor, said second field - effect transistor having its conduction path electrodes interconnected between said second common point and a first end of said second resistor and its gate electrode connected to a second end of said second resistor, said first varistor having its one end connected also to said first common point and its other end connected to said first output terminal, said second varistor having its one end connected also to said second common point and its other end connected to said second output terminal.   
     
     
       39. The filter circuit of  claim 35 , further comprising:
   at least one third inductor disposed electrically between said first common point and said current limiter; and        at least one fourth inductor disposed electrically between said second common point and said current limiter.     
     
     
       40. The filter circuit of  claim 35 , wherein said circuit is adapted for interconnection between incoming telephone lines and a customer's terminal equipment and configured so as to unconditionally block impedances from above  20  KHz associated with the customer's terminal equipment from an ADSL network unit and/or home networking interface unit. 
     
     
       41. An impedance blocking DSL filter circuit, comprising:
   a plurality of first line side terminals;        a plurality of second equipment side terminals;        a plurality of common points disposed electrically between respective ones of said first and second terminals;        a first filter stage disposed electrically between said first terminals and said common points;        a second filter stage disposed electrically between said common points and said second terminals, said second stage comprising at least one substantially transistorized current limiter; and        a capacitance disposed electrically between said common points.     
     
     
       42. The filter circuit of  claim 41 , further comprising a third filter stage disposed between said common points and said second filter stage. 
     
     
       43. The filter circuit of  claim 41 , wherein said first filter stage comprises a first and second plurality of inductors, said first and second pluralities of inductors each being disposed in electrical series between first and second ones of said input terminals and common points, respectively. 
     
     
       44. The filter circuit of  claim 43 , wherein said second filter stage comprises first and second resistors. 
     
     
       45. The filter circuit of  claim 41 , wherein said first and second filter stages are configured to at least partly block impedances in first and second frequency bands, respectively. 
     
     
       46. The filter circuit of  claim 45 , wherein said first band is approximately  30  kHz to  2  MHz, and said second band is approximately  20  kHz to  60  kHz. 
     
     
       47. The filter circuit of  claim 41 , wherein said first filter stage comprises at least a plurality of ferrite toroids. 
     
     
       48. An impedance blocking DSL filter circuit, comprising:
   a plurality of first line side terminals;        a plurality of second equipment side terminals;        a plurality of common points disposed electrically between respective ones of said first and second terminals;        a first filter stage disposed electrically between said first terminals and said common points, said first filter stage comprising a plurality of inductors, at least two of said plurality of inductors being formed as separate inductors so as to at least partly block differential impedances;        a second stage disposed electrically between said common points and said second terminals, said second stage comprising a plurality of varistors; and        a capacitance disposed electrically between said common points.     
     
     
       49. An impedance blocking DSL filter circuit, comprising:
   a plurality of first line side terminals;        a plurality of second equipment side terminals;        a plurality of common points disposed electrically between respective ones of said first and second terminals;        a first filter stage disposed electrically between said first terminals and said common points and adapted to block impedances in a first band, said first filter stage comprising a plurality of inductors, at least two of said plurality of inductors being formed as separate inductors so as to at least partly block differential impedances;        a second filter stage disposed electrically between said common points and said second terminals and adapted to block impedances in a second band, said second stage comprising a plurality of resistors; and        a capacitance disposed electrically between said common points, said capacitance being adapted to displace resonance generated within said circuit to a third band.     
     
     
       50. An impedance blocking filter circuit used in telecommunication systems for interconnecting between incoming telephone lines and customer's terminal equipment so as to unconditionally block impedances from above  20  KHz due to the customer's terminal equipment from an ADSL network unit and/or home networking interface unit, said filter circuit comprising:
   first, second, and third inductors connected in series between a first input terminal corresponding to said incoming telephone lines and a first common point;        said first inductor having its one end connected to said first input terminal and its other end connected to one end of said second inductor, said second inductor having its other end connected to one end of said third inductor, said third inductor having its other end connected to said first common point;        a first resistor having its one end also connected to said first common point and its other end connected to a first output terminal;        fourth, fifth, and sixth inductors connected in series between a second input terminal and a second common point;        said four inductor having its one end connected to said second input terminal and its other end connected to one end of said fifth inductor, said fifth inductor having its other end connected to one end of said sixth inductor, said sixth inductor having its other end connected to said second common point;        a second resistor having its one end also connected to said second common point and its other end connected to a second output terminal; and        a capacitor having its one end connected to said first common point and its other end connected to said second common point.     
     
     
       51. An impedance blocking filter circuit used in telecommunication systems for interconnecting between incoming telephone lines and customer's terminal equipment so as to unconditionally block impedances from above  20  KHz due to the customer's terminal equipment from an ADSL network unit and/or home networking interface unit, said filter circuit comprising:
   first, second, and third inductors connected in series between a first input terminal corresponding to said incoming telephone lines and a first common point;        said first inductor having its one end connected to said first input terminal and its other end connected to one end of said second inductor, said second inductor having its other end connected to one end of said third inductor, said third inductor having its other end connected to said first common point;        a seventh inductor and a first resistor connected in series between said first common point and a first output terminal, said seventh inductor having its one end connected also to said first common point and its other end connected to one end of said first resistor, said first resistor having its other end connected to a first output terminal;        fourth, fifth, and sixth inductors connected in series between a second input terminal and a second common point;        said four inductor having its one end connected to said second input terminal and its other end connected to one end of said fifth inductor, said fifth inductor having its other end connected to one end of said sixth inductor, said sixth inductor having its other end connected to said second common point;        an eighth inductor and a second resistor connected in series between said second common point and a second output terminal, said eighth inductor having its one end connected also to said second common point and its other end connected to one end of said second resistor, said second resistor having its other end connected to a second output terminal; and        a capacitor having its one end connected to said first common point and its other end connected to said second common point.     
     
     
       52. An impedance blocking filter circuit as claimed in  claim 50 , wherein said first and fourth inductors are comprised of ferrite toroids. 
     
     
       53. An impedance blocking filter circuit as claimed in  claim 52 , wherein said second and fifth inductors have values on the order of  220  μH. 
     
     
       54. An impedance blocking filter circuit as claimed in  claim 53 , wherein said third and sixth inductors have values on the order of  10  mH. 
     
     
       55. An impedance blocking filter circuit as claimed in  claim 54 , wherein said first and second resistors have values on the order of  22  Ohms. 
     
     
       56. An impedance blocking filter circuit as claimed in  claim 55 , wherein said capacitor has the value on the order of  22  nf. 
     
     
       57. An impedance blocking circuit as claimed in  claim 50 , further comprising current limiting protection means connected between said common points and said output terminals for reducing current spikes caused by the customer's terminal equipment going off- hook.   
     
     
       58. An impedance blocking filter circuit as claimed in  claim 57 , wherein said current limiting protection means is comprised of first and second depletion mode field- effect transistors and first and second transient protection varistors.   
     
     
       59. An impedance blocking filter circuit as claimed in  claim 58 , wherein said first depletion mode field- effect transistor has its conduction path electrodes interconnected between said first common point and said one end of said first resistor and its gate electrode connected to said other end of said first resistor, said second depletion mode field - effect transistor having its conduction path electrodes interconnected between said second common point and said one end of said second resistor and its gate electrode connected to said other end of said second resistor, said first varistor having its one end connected also to said first common point and its other end connected to said first output terminal, said second varistor having its one end connected also to said second common point and its other end connected to said second output terminal.   
     
     
       60. An impedance blocking filter circuit as claimed in  claim 51 , wherein said first and fourth inductors are comprised of ferrite toroids. 
     
     
       61. An impedance blocking filter circuit as claimed in  claim 60 , wherein said second and fifth inductors have values on the order of  220  μH. 
     
     
       62. An impedance blocking filter circuit as claimed in  claim 61 , wherein said third and sixth inductors have values on the order of  5 - 10  mH. 
     
     
       63. An impedance blocking filter circuit as claimed in  claim 62 , wherein said seventh and eighth inductors have values on the order of  5 - 10  mH. 
     
     
       64. An impedance blocking filter circuit as claimed in  claim 63 , wherein said first and second resistors have values on the order of  22  Ohms. 
     
     
       65. An impedance blocking filter circuit as claimed in  claim 64 , wherein said capacitor has the value on the order of  47  nf. 
     
     
       66. An impedance blocking filter circuit as claimed in  claim 51 , further comprising home network demarcation filter means interconnected between the incoming telephone lines and internal house wiring for blocking the impedance of the customer's terminal equipment from home networking signals. 
     
     
       67. An impedance blocking filter circuit as claimed in  claim 66 , said demarcation filter means is comprised of six inductors and two capacitors. 
     
     
       68. An impedance blocking filter circuit as claimed in  claim 51 , further comprising home network demarcation filter means interconnected between the incoming telephone lines and internal house wiring for blocking the impedance of the customer's terminal equipment from home networking signals. 
     
     
       69. An impedance blocking filter circuit as claimed in  claim 68 , said demarcation filter means is comprised of six inductors and two capacitors. 
     
     
       70. An impedance blocking filter circuit used in telecommunication systems for interconnecting between incoming communications lines and customer's terminal equipment so as to attenuate at least some impedances above  20  KHz due to the customer's terminal equipment, said filter circuit comprising:
   first, second, and third inductors disposed in electrical series between a first input terminal corresponding to said incoming telephone lines and a first common point;        a first resistor having its one end also in electrical communication with said first common point and its other end in electrical communication with a first output terminal;        fourth, fifth, and sixth inductors disposed in electrical series between a second input terminal and a second common point;        a second resistor having its one end also in electrical communication with said second common point and its other end in electrical communication with a second output terminal; and        a capacitor having its one end in electrical communication with said first common point and its other end in electrical communication with said second common point.     
     
     
       71. An impedance blocking filter circuit used in telecommunication systems for interconnecting between incoming communications lines and customer's terminal equipment so as to attenuate at least some impedances above  20  KHz due to the customer's terminal equipment, said filter circuit comprising:
   first, second, and third inductors disposed in electrical series between a first input terminal corresponding to said incoming telephone lines and a first common point;        a seventh inductor and a first resistor disposed in electrical series between said first common point and a first output terminal, said seventh inductor having its one end in electrical communication with said first common point and its other end in electrical communication with one end of said first resistor, said first resistor having its other end in electrical communication with a first output terminal;        fourth, fifth, and sixth inductors disposed in electrical series between a second input terminal and a second common point;        an eighth inductor and a second resistor disposed in electrical series between said second common point and a second output terminal, said eighth inductor having its one end in electrical communication with said second common point and its other end in electrical communication with one end of said second resistor, said second resistor having its other end in electrical communication with a second output terminal; and        a capacitor having its one end in electrical communication with said first common point and its other end in electrical communication with said second common point.     
     
     
       72. A telecommunications filter circuit comprising:
   at least one first inductor electrically disposed between a first input terminal and a first common point;        at least one second inductor electrically disposed between a second input terminal and a second common point;        at least one capacitor disposed electrically between said first and second common points; and        a current limiter disposed electrically between said first and second common points and first and second output terminals, said current limiter comprising first and second field - effect transistors, first and second varistors, and first and second resistors, said first field - effect transistor having its conduction path electrodes interconnected between said first common point and a first end of said first resistor and its gate electrode connected to a second end of said first resistor, said second field - effect transistor having its conduction path electrodes interconnected between said second common point and a first end of said second resistor and its gate electrode connected to a second end of said second resistor, said first varistor having its one end connected also to said first common point and its other end connected to said first output terminal, said second varistor having its one end connected also to said second common point and its other end connected to said second output terminal.     
     
     
       73. A telecommunications filter circuit comprising:
   at least one first inductor electrically disposed between a first input terminal and a first common point;        at least one second inductor electrically disposed between a second input terminal and a second common point;        at least one capacitor disposed electrically between said first and second common points; and        a current limiter disposed electrically between said first and second common points and first and second output terminals, said current limiter comprising first and second transistors, first and second varistors, and first and second resistors, said first transistor having its conduction path electrodes disposed electrically between said first common point and a first end of said first resistor and its gate electrode electrically communicating with a second end of said first resistor, said second transistor having its conduction path electrodes disposed electrically between said second common point and a first end of said second resistor and its gate electrode electrically communicating with a second end of said second resistor, said first varistor having its one end electrically communicating with said first common point and its other end electrically communicating with said first output terminal, said second varistor having its one end electrically communicating with said second common point and its other end electrically communicating said second output terminal.     
     
     
       74. A telecommunications filter circuit comprising:
   at least one first inductor electrically disposed between a first input terminal and a first common point;        at least one second inductor electrically disposed between a second input terminal and a second common point;        at least one capacitor disposed electrically between said first and second common points; and        a current limiter disposed electrically between said first and second common points and first and second output terminals, said current limiter comprising first and second transistors, first and second varistors, and first and second resistors, said first transistor having its conduction path electrodes disposed electrically between said first common point and a first end of said first resistor, said second transistor having its conduction path electrodes disposed electrically between said second common point and a first end of said second resistor, said first varistor having its one end electrically communicating with said first common point and its other end electrically communicating with said first output terminal, said second varistor having its one end electrically communicating with said second common point and its other end electrically communicating said second output terminal.