Device for extracting parameters for decoding a video data flow coded according to an MPEG standard

Abstract

A device for extracting parameters for decoding a video data flow, contained in headers preceded by a starting code of series of data coded according to an MPEG standard, organized, independently and according to the starting code, and storage of the parameters in three register banks.

1. In a computer system having a processor executing at least one application program and a video decoder decoding a  video data for display, an extraction circuit for extracting from the video data a plurality of header data each associated with one of a plurality of starting code types, the extraction circuit comprising:
 a starting code detector receiving the video data, and operable to detect a starting code contained in the video data while the processor is executing the application program and operable to prevent an interrupt from being passed to the processor when a starting code is detected;  
 a branch circuit having an input connected to the starting code detector, and operable to branch the header data associated with the detected starting code type, and  
 a plurality of register units connected to the branch circuit for receiving the branched header data, each register unit being associated with one of the plurality of starting code types and each operable to store the header data associated with the register unit ;  
 wherein the branch circuit includes means for recognizing the occurrence of quantization tables in the video data and for branching the data relative to these tables to a circuit for restoring quantization arrays,  
 wherein the branch circuit is associated with a calculator for converting the header,  data prior to their storage in one of the register units,  into instructions directly interpretable by a video decoder and accessible in any order by a microprocessor; and  
 wherein the starting code detector generates an interrupt for the processor when all header data are stored in the plurality of register units.  
 
     
     
       2. The extraction circuit according to  claim 1 , further comprising a calculator connected to the branch circuit and the plurality of register units, and operable to convert the header data into parameters usable by the video decoder and  wherein each register unit stores the parameters  is associated with one of the plurality of starting code types and is operable to store header data associated with the register unit, wherein the calculator is connected to the plurality of register units, and is operable to convert the header data into parameters usable by the video decoder and each register unit stores the parameters associated with the register unit. 
     
     
       3. The extraction circuit according to claim  1    2  wherein the plurality of register units includes  3  three  register units respectively storing information related to a sequence header, group header and image header. 
     
     
       4. In a computer system having an application processor executing at least one application program and a video decoder decoding a video bitstream data for display, an extraction circuit for extracting from the video bitstream data a plurality of header data each associated with one of a plurality of header code types, the extraction circuit comprising,
 a plurality of register units each associated with one of the plurality of header code types; and  
 a header processor having an input receiving the video bitstream data and an output connected to the plurality of register units, the header processor operable to detect a header code contained in the video bitstream data and upon detection route the associated header data to its output for storage by the register unit associated with the detected header code type, the header processor performing the detection and routing while the application processor is executing the application program; wherein the header processor includes: 
 means for recognizing the occurrence of quantization tables in the data flow and for branching the data relative to these tables to a circuit for restoring quantization arrays,  
 a calculator for converting the data contained in the headers, prior to their storage in one of the register units, into instructions directly interpretable by a video decoder and accessible in any order by a microprocessor; and  
 a starting code detector that generates an interrupt for the application processor when all header data are stored in the plurality of register units.  
 
 
     
     
       5. In a computer system having a processor executing a plurality of programs and a video decoder decoding a video data for display, a method of extracting from the video data a plurality of header data each associated with a starting code, the method comprising the steps of:
 receiving the video data containing the plurality of header data and the associated starting codes;  
 repeating the following steps at least two times independent of the processor: 
 detecting a starting code in the received video data;  
 routing the associated header data to an associated one of a plurality of register units according to the detected starting code type; and storing the associated header data in the associated register unit;  
 
 recognizing the occurrence of quantization tables in the video data and branching the data relative to these tables to a circuit for restoring quantization arrays;  
 converting the header data, prior to their storage in one of the register units, into instructions directly interpretable by a video decoder and accessible in any order by a microprocessor, and  
 interrupting the processor when all header data are stored in the plurality of register units.  
 
     
     
       6. The method according to  claim 5 , prior to the step of storing, further comprising the step of converting the associated header data into parameters usable by the video decoder wherein each register unit stores the parameters of the associated header data. 
     
     
       7. A device for extracting parameters for decoding a video data flow, contained in headers coded according to an MPEG standard, said headers being preceded by a starting code, said device comprising:
 means for organizing, independently and according to the starting code, a storage of the parameters in  three register banks for storing the parameters;  
 a starting code detector, implemented in wired logic ;  
 a state machine, associated with the starting code detector, for branching the contents of the headers to the register banks according to the starting code detected;  wherein the state machine includes means for recognizing the occurrence of quantization tables in the data flow and for branching the data relative to thee tables to a circuit for restoring quantization arrays;  
 a calculator, associated with the state machine, for converting the data contained in the headers, prior to their storage in one of the three register banks, into instructions directly interpretable by a video decoder and accessible in any order by a microprocessor; and  
 wherein, in an automatic operating mode, the detector generates an interrupt for the microprocessor, only when all decoding parameters have been stored in the three register banks.  
 
     
     
       8. A device according to  claim 7  wherein the detector is associated with a status register, accessible by a microprocessor and meant for containing the starting code detected. 
     
     
       9. A device according to  claim 8  wherein the detector is associated with interrupt and stop registers for configuring its operating mode. 
     
     
       10. A device according to  claim 9  wherein, in a manual operating mode, the detector generates an interrupt for the microprocessor, upon each occurrence of a starting code in the data flow. 
     
     
       11. The extraction circuit according to  claim 4  wherein the plurality of register units includes three register units respectively storing information related to a sequence header, group header, and image header. 
     
     
       12. The extraction circuit according to  claim 4 , further comprising a status register, associated with wherein the header processor, accessible by a microprocessor, and meant for containing the starting code detected. 
     
     
       13. The extraction circuit according to  claim 4  further comprising interrupt and stop registers, associated with the header processor, for configuring its operating mode. 
     
     
       14. The extraction circuit according to  claim 4  wherein, in a manual operating mode, the header processor generates an interrupt for the microprocessor, upon each occurrence of a starting code in the data flow. 
     
     
       15. The device of  claim 7  wherein said headers are preceded by a starting code, the device further comprising:
   means for organizing, independently and according to the starting code, a storage of the parameters in a plurality of register banks;        wherein the starting code detector is implemented in wired logic; and        wherein the state machine is for branching the contents of the headers to the register banks according to the starting code detected.