Method of fabricating a semiconductor device

Abstract

The present invention relates to a method of fabricating a semiconductor device which reducesThe leakage current by controlling an etch of a field oxide layer when a contact hole is formed. The present invention includes the steps of forming ain a semiconductor device is reduced. A field oxide layer defining an active area and a field areais formed on a semiconductor substrateof a first conductive type, forming a. A gate is formed on thean active area of the semiconductor substrate. by inserting a gate insulating layer between the semiconductor substrate and the gate, forming impurity regions of a second conductive type in the semiconductorare formed on the substrate in use ofusing the gate as a mask, forming a. A first insulating interlayerlayer is formed on the semiconductor substrate by depositing an insulator of whichhaving the heat expansion coefficient and lattice mismatch that are less than those of the semiconductor substrateto cover the field oxide layer and the gate, forming a. A second insulating interlayerlayer is formed on the first insulating interlayerlayer by depositing another insulator of whichhaving an etch rate that is different from that of the first insulating interlayer, forming alayer. A third insulating interlayerlayer is formed on the second insulating interlayerlayer by depositing yet another insulator of whichhaving an etch rate that is different from that of the second insulating interlayer, and forming a first contact holelayer. First and second contact holes exposing the gate and heavily doped regions respectivelyare formed by patterning the third to first insulating interlayer successively by photolithographylayers.

1. A method of fabricating a semiconductor device comprising the steps of:
 forming a field oxide layerdefining , which defines an active area and a field area on a semiconductor substrate of a first conductive type;  
 forming a gate on the active area of the semiconductor substrate by inserting a gate insulating layer between the semiconductor substrate and the gate;  
 forming impurity regions of a second conductive type in the semiconductor substrate in use of  using the gate as a mask;  
 forming a first insulating interlayer  layer on the semiconductor substrate by depositing an insulator of which heat expansion coefficient and lattice mismatch are less than those of the semiconductor substrate to cover the field oxide layer and the gate;  
 forming a second insulating interlayer  layer on the first insulating interlayer  layer by depositing another insulator of which an etch rate is different from that of the first insulating interlayer  layer;  
 forming a third insulating interlayer  layer on the second insulating interlayer  layer by depositing still another insulator of which an etch rate is different from that of the second insulating interlayer  layer; and  
 forming a first contact hole and second contact holes respectively exposing the gate and heavily doped  impurity regions respectively  by successively patterning the third to first insulating interlayer successively by  layers through photolithography,  
   wherein the second insulating layer is etched by C   2   HF   6   O   2   , and    
   wherein the successive patterning of the third to first insulating layers excludes portions of the third to first insulating layers formed above the field oxide layer such that the portions of the third to first insulating layers formed above the field oxide layer prevent the etching of the field oxide layer.    
 
     
     
       2. The method of fabricating a semiconductor device according to  claim 1 , wherein the field oxide layer is formed by shallow trench isolation or by local oxidation of silicon. 
     
     
       3. The method of fabricating a semiconductor device according to  claim 1 , wherein the first insulating interlayer  layer is formed by depositing silicon oxide to a thickness of 100 to  300 Åthick .    
     
     
       4. The method of fabricating a semiconductor device according to  claim 3 , wherein the first insulating interlayer  layer is etched by a mixed gas of (C2F6+O2) or (C4F8+O2)  ( C   2   F   6   +O   2 )  or  ( C   4   F   8   +O   2 ). 
     
     
       5. The method of fabricating a semiconductor device according to  claim 1 , wherein the second insulating interlayer  layer is formed by depositing silicon nitride to a thickness of 100 to  300 Åthick .    
     
     
       6. The method of fabricating a semiconductor device according to  claim 5 , wherein the second insulating interlayer is etched by C2HF6O2. 
     
     
       7. The method of fabricating a semiconductor device according to  claim 1 , wherein the third insulating interlayer  layer is formed by depositing silicon oxide or boro phospho silicate glass or by coating with  spin on glass. 
     
     
       8. The method of fabricating a semiconductor device according to  claim 7 , wherein the third insulating interlayer of a single  layer is formed with one or more layers made of silicon oxide, boro phospho silicate glass, or spin on glassor wherein the third insulating interlayer of at least double layers is formed with silicon oxide, boro phospho silicate glass and spin on glass . 
     
     
       9. The method of fabricating a semiconductor device according to  claim 7 , wherein a surface of the third insulating interlayer  layer is formed to be even. 
     
     
       10. The method of fabricating a semiconductor device according to  claim 7 , wherein the third insulating interlayer  layer is etched by a mixed gas of (C2F6+O2) or (C4F8+O2)  ( C   2   F   6   +O   2 )  or  ( C   4   F   8   +O   2 ). 
     
     
       11. The method of fabricating a semiconductor device according to  claim 10 , wherein the third insulating interlayer  layer is overetched  over- etched  to expose the second insulating interlayer  layer corresponding to the heavily doped  impurity regions. 
     
     
       12. The method of fabricating a semiconductor device according to  claim 1 , the method  further comprising the step of forming first and second plugs in the first and second contact holes. 
     
     
       13. A method of fabricating a semiconductor device comprising the steps of
 forming a field oxide layer defining  which defines an active area and a field area on a semiconductor substrate of a first conductive type;  
 forming a gate on the active area of the semiconductor substrate by inserting a gate insulating layer between the semiconductor substrate and the gate;  
 forming a sidewall spacer at a side of the gate; 
 forming lightly doped regions of a second conductive type in exposed portions of the semiconductor substrate;  
 forming a sidewall spacer at a side of the gate; 
 forming heavily doped regions of the second conductive type in the semiconductor substrate in use of  using the gate and sidewall spacer as a mask wherein  so that the heavily doped regions are overlapped with the lightly doped regions;  
 forming a first insulating interlayer  layer on the semiconductor substrate by depositing an insulator of which heat expansion coefficient and lattice mismatch are less than those of the semiconductor substrate to cover the field oxide layer and the gate;  
 forming a second insulating interlayer  layer on the first insulating interlayer  layer by depositing another insulator of which an etch rate is different from that of the first insulating interlayer  layer;  
 forming a third insulating interlayer  layer on the second insulating interlayer  layer by depositing still another insulator of which an etch rate is different from that of the second insulating interlayer  layer;  
 forming a first contact hole  first and second contact holes respectively exposing the gate and heavily doped regions respectively  by successively patterning the third to first insulating interlayer successively by  layers through photolithography; and  
 forming first and second plugs in the first and second contact holes,  
   wherein the second insulating layer is etched by C   2   HF   6   O   2   , and    
   wherein the successive patterning of the third to first insulating layers excludes portions of the third to first insulating layers formed above the field oxide layer such that the portions of the third to first insulating layers formed above the field oxide layer prevent the etching of the field oxide layer.    
 
     
     
       14. A method of fabricating a semiconductor device comprising the steps of:
   forming a field oxide layer, which defines an active area and a field area on a semiconductor substrate of a first conductive type;        forming a gate on the active area of the semiconductor substrate by inserting a gate insulating layer between the semiconductor substrate and the gate;        forming impurity regions of a second conductive type in the semiconductor substrate using the gate as a mask;        forming a first insulating layer on the semiconductor substrate by depositing an insulator of which heat expansion coefficient and lattice mismatch are less than those of the semiconductor substrate to cover the field oxide layer and the gate;        forming a second insulating layer on the first insulating layer by depositing another insulator of which an etch rate is different from that of the first insulating layer;        forming a third insulating layer on the second insulating layer by depositing still another insulator of which an etch rate is different from that of the second insulating layer, the third insulating layer comprising two or more layers among silicon oxide, boro phospho silicate glass, and spin on glass; and        forming a first contact hole and second contact holes respectively exposing the gate and impurity regions by successively patterning the third to first insulating layers through photolithography,        wherein the successive patterning of the third to first insulating layers excludes portions of the third to first insulating layers formed above the field oxide layer such that the portions of the third to first insulating layers formed above the field oxide layer prevent the etching of the field oxide layer.     
     
     
       15. The method of fabricating a semiconductor device according to  claim 14 , wherein the field oxide layer is formed by shallow trench isolation or by local oxidation of silicon. 
     
     
       16. The method of fabricating a semiconductor device according to  claim 14 , wherein the first insulating layer is formed by depositing silicon oxide to a thickness of  100  to  300  Å. 
     
     
       17. The method of fabricating a semiconductor device according to  claim 16 , wherein the first insulating layer is etched by a mixed gas of ( C   2   F   6   +O   2 )  or  ( C   4   F   8   +O   2 ). 
     
     
       18. The method of fabricating a semiconductor device according to  claim 14 , wherein the second insulating layer is formed by depositing silicon nitride to a thickness of  100  to  300  Å. 
     
     
       19. The method of fabricating a semiconductor device according to  claim 18 , wherein the second insulating layer is etched by C 2   HF   6   O   2 . 
     
     
       20. The method of fabricating a semiconductor device according to  claim 14 , wherein the third insulating layer is formed by depositing silicon oxide or boro phospho silicate glass or by coating spin on glass. 
     
     
       21. The method of fabricating a semiconductor device according to  claim 20 , wherein a surface of the third insulating layer is formed to be even. 
     
     
       22. The method of fabricating a semiconductor device according to  claim 20 , wherein the third insulating layer is etched by a mixed gas of ( C   2   F   6   +O   2 )  or  ( C   4   F   8   +O   2 ). 
     
     
       23. The method of fabricating a semiconductor device according to  claim 22 , wherein the third insulating layer is over- etched to expose the second insulating layer corresponding to the impurity regions.   
     
     
       24. The method of fabricating a semiconductor device according to  claim 14 , further comprising the step of forming first and second plugs in the first and second contact holes. 
     
     
       25. A method of fabricating a semiconductor device comprising the steps of
   forming a field oxide layer which defines an active area and a field area on a semiconductor substrate of a first conductive type;        forming a gate on the active area of the semiconductor substrate by inserting a gate insulating layer between the semiconductor substrate and the gate;        forming lightly doped regions of a second conductive type in exposed portions of the semiconductor substrate;        forming a sidewall spacer at a side of the gate;        forming heavily doped regions of the second conductive type in the semiconductor substrate using the gate and sidewall spacer as a mask so that the heavily doped regions are overlapped with the lightly doped regions;        forming a first insulating layer on the semiconductor substrate by depositing an insulator of which heat expansion coefficient and lattice mismatch are less than those of the semiconductor substrate to cover the field oxide layer and the gate;        forming a second insulating layer on the first insulating layer by depositing another insulator of which an etch rate is different from that of the first insulating layer;        forming a third insulating layer on the second insulating layer by depositing still another insulator of which an etch rate is different from that of the second insulating layer, the third insulating layer comprising two or more layers among silicon oxide, boro phospho silicate glass, and spin on glass;        forming first and second contact holes respectively exposing the gate and heavily doped regions by successively patterning the third to first insulating layers through photolithography; and        forming first and second plugs in the first and second contact holes,        wherein the successive patterning of the third to first insulating layers excludes portions of the third to first insulating layers formed above the field oxide layer such that the portions of the third to first insulating layers formed above the field oxide layer prevent the etching of the field oxide layer.