Phase locked loop circuit

Abstract

A PLL circuit comprises a frequency comparator for detecting a phase difference based on a difference in frequencies between a reproduced data pulse and a clock generated by a VCO; a phase comparator for detecting a difference in phases between the reproduced data pulse and the VCO clock; a selector for selectively outputting a signal supplied from the frequency comparator, a first charge pump for increasing/decreasing the output voltage on the basis of the output from the selector; a second charge pump for increasing/decreasing the output voltage on the basis of the output from the phase comparator; a loop filter for eliminating unnecessary components included in a signal obtained by adding the output from the first charge pump and the output from the second charge pump; and a VCO for generating a clock of a frequency corresponding to the output voltage of the loop filter. In this PLL circuit, when the phase difference between the reproduced data pulse and the VCO clock is within the pull-in range of the phase comparator, the operation of the frequency comparator is restricted by the output of the phase comparator. Therefore, the PLL circuit can perform stable data reading even when the reproduced data pulse has a large amount of clock jitter.

1. A phase locked loop circuit, for use in a magnetic disk unit that generates a clock signal in phase-synchronization with a reproduced data pulse read from a magnetic disk, said phase locked loop circuit comprising:
 a frequency comparator operable to detect a difference in frequencies between the reproduced data pulse and the clock signal, and to output a frequency comparison error signal based on the difference, said frequency comparison error signal indicating a frequency error level;    a phase comparator operable to detect a difference in phases between the reproduced data pulse and the clock signal and to produce an output based on the difference;    a selector operable to output said frequency comparison error signal when the frequency error level indicated by said frequency comparison error signal is greater than or equal to a predetermined value and to prevent outputting of said frequency comparison error signal when the frequency error level indicated by said frequency comparison error signal is less than the predetermined value;    a first charge pump operable to output a first voltage, and to increase or decrease the first voltage based on the output of said selector;    a second charge pump operable to output a second voltage, and to increase or decrease the second voltage based on the output of said comparator;    a loop filter operable to eliminate unnecessary components included in a sum of the outputs of said first and second charge pumps and to produce a filtered output voltage; and    a voltage controlled oscillator operable to generate a clock of a frequency corresponding to the filtered output voltage from said loop filter.    
     
     
       2. A phase locked loop circuit according to  claim 1  wherein:
 the clock signal has phase sections;    said frequency comparator is operable to detect which phase section of the clock signal corresponds to a leading edge of the reproduced data pulse and which phase section corresponds to a trailing edge of the reproduced data pulse, compare the phase section of the clock signal that corresponds to the leading edge of the reproduced data pulse and the phase section of the clock signal that corresponds to the trailing edge of the reproduced data pulse, and to output a result of the comparison as a frequency comparison error signal; and    said selector does not output the frequency comparison error signal when the phase section that corresponds to the leading edge of the reproduced data pulse and the phase section that corresponds to the trailing edge of the reproduced data pulse are detected by said frequency comparator to be specific predetermined values.    
     
     
       3. A phase locked loop circuit for generating a clock signal in phase- synchronization with an input data pulse, said phase locked loop circuit comprising:      a frequency comparator operable to detect a difference in frequencies between the input data pulse and the clock signal, and to output a frequency comparison error signal based on the difference, the frequency comparison error signal indicating a frequency error level; and        an output selectable circuit operable to output the frequency comparison error signal when the frequency error level indicated by the frequency comparison error signal is greater than or equal to a predetermined value and to prevent outputting of the frequency comparison error signal when the frequency error level indicated by the frequency comparison error signal is less than the predetermined value, wherein:        said frequency comparator is operable to detect the difference by checking a phase section of the clock signal at an edge of the input data pulse.      
     
     
       4. A phase locked loop circuit according to  claim 3 , wherein:
   the phase section is detected corresponding to a leading edge and a trailing edge of the input data pulse.