Multi-state EEPROM having write-verify control circuit

Abstract

An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plurality of memory cells, a write circuit for performing a write operation in accordance with the contents of the data circuits respectively corresponding to the memory cells, a write verify circuit for confirming states of the memory cells set upon the write operation, and a data updating circuit for updating the contents of the data circuits such that a rewrite operation is performed to only a memory cell, in which data is not sufficiently written, on the basis of the contents of the data circuits and the states of the memory cells set upon the write operation. A write operation, a write verify operation, and a data circuit content updating operation based on the contents of the data circuits are repeatedly performed until the memory cells are set in predetermined written states.

1. A multi-level non-volatile semiconductor memory device comprising:
 a semiconductor substrate;    a plurality of bit lines;    a plurality of word lines insulatively intersecting said bit lines;    a memory cell array comprising a plurality of memory cells coupled to said word lines and bit lines, each memory cell including a transistor with a charge storage portion and having written states of first, second, . . . , (n−1)th and nth (n≧3) predetermined storage levels;    a plurality of programming control circuits coupled to said memory cell array for storing data of first, second, . . . , (n−1)th and nth predetermined logic levels in data storage portions which define write voltages to be applied to respective of said memory cells, for applying said write voltages to said respective of said memory cells according to the data stored in said data storage portions, for determining actual written states of said memory cells, for modifying stored data from said ith (i=2, 3, . . . , n−1, n) predetermined logic level to said first predetermined logic level in the data storage portions storing the data of said ith (respectively, i=2, 3, . . . , n−1, n) predetermined logic level and corresponding to the memory cells in which successful writing of said ith (respectively, i=2, 3, . . . , n−1, n) predetermined storage data has been determined, for maintaining said stored state at said ith (i=2, 3, . . . , n−1, n) predetermined logic level in the data storage portions storing the data of said ith (respectively, i=2, 3, . . . , n−1, n) predetermined logic level and corresponding to the memory cells in which it has been determined that said ith (respectively, i=2, 3, . . . , n−1, n) predetermined storage level has not been successfully written, and for maintaining said stored data at said first predetermined logic level in the data storage portions storing the data of said first predetermined logic level.    
     
     
       2. The device according to  claim 1 , wherein said data stored in said data storage portions are initially set to initial data, and then said initial data stored in said data storage portions are modified. 
     
     
       3. The device according to  claim 2 , wherein said initial data are loaded from at least one input line coupled to said data storage portions. 
     
     
       4. The device according to  claim 1 , wherein said actual written states of said memory cells corresponding to the data storage portions storing the data of said ith (i=2, 3, . . . , n−1, n) predetermined logic level are simultaneously determined. 
     
     
       5. The device according to  claim 1 , wherein said actual written states of said memory cells corresponding to the data storage portions storing the data of said second, third, . . . , (n−1)th and nth predetermined logic levels are simultaneously determined. 
     
     
       6. The device according to  claim 1 , wherein said data of said ith (i=2, 3, . . . , n−1, n) predetermined logic level stored in the data storage portions corresponding to the memory cells in which successful writing has been determined are simultaneously modified to the data of said first predetermined logic level. 
     
     
       7. The device according to  claim 1 , wherein said data of said second, third, . . . , (n−1)th and nth predetermined logic levels stored in the data storage portions corresponding to the memory cells in which successful writing has been determined are simultaneously modified to the data of said first predetermined logic level. 
     
     
       8. The device according to  claim 1 , further comprising a plurality of data write end detection circuits coupled to said data storage portions for simultaneously detecting whether or not all of said data storage portions store the data of said first predetermined logic level. 
     
     
       9. The device according to  claim 8 , wherein each of said data write end detection circuits is provided for each of said data storage portions. 
     
     
       10. The device according to  claim 9 , wherein said data write end detection circuits are coupled to at least one common output line, and said data write end detection circuits output a programming completion signal on said common output line when each data storage portion stores the data of said first predetermined logic level. 
     
     
       11. The device according to  claim 10 , wherein said applying, determining and modifying are continued until said data write end detection circuits output said programming completion signal. 
     
     
       12. The device according to  claim 1 , wherein said applying, determining and modifying are continued until each memory cell is sufficiently written. 
     
     
       13. The device according to  claim 1 , wherein said write voltages are simultaneously applied to said respective of said memory cells. 
     
     
       14. The device according to  claim 13 , wherein said write voltages defined by said data stored in said data storage portions and applied to said respective of said memory cells differ according to said data stored in said data storage portions. 
     
     
       15. The device according to  claim 1 , wherein said programming control circuits are arranged adjacent to said memory cell array. 
     
     
       16. The device according to  claim 1 , wherein each of said programming control circuits is connected to a respective one of said bit lines. 
     
     
       17. The device according to  claim 1 , wherein said programming control circuits include bit line voltage regulators for selectively changing voltages of said bit lines according to said data stored in said data storage portions. 
     
     
       18. The device according to  claim 17 , wherein said voltages of said bit lines are selectively and simultaneously changed by said bit line voltage regulators. 
     
     
       19. A multi-level non-volatile semiconductor memory device comprising:
 a semiconductor substrate;    a plurality of bit lines;    a plurality of word lines insulatively intersecting said bit lines;    a memory cell array comprising a plurality of memory cells coupled to said word lines and bit lines, each memory cell including a transistor with a charge storage portion and having written states of first, second, . . . , (n−1)th and nth (n≧3) predetermined storage levels;    a plurality of programming control circuits coupled to said memory cell array for storing data of first, second, . . . , (n−1)th and nth predetermined logic levels in data storage portions which define write voltages to be applied to respective of said memory cells, said data being initially set to initial data which are loaded from at least one input line coupled to said data storage portions, for applying said write voltages to said respective of said memory cells according to the data stored in said data storage portions, for determining actual written states of said memory cells, for modifying stored data from said ith (i=2, 3, . . . , n−1, n) predetermined logic level to said first predetermined logic level in the data storage portions storing the data of said ith (respectively, i=2, 3, . . . , n−1, n) predetermined logic level and corresponding to the memory cells in which successful writing of said ith (respectively, i=2, 3, . . . , n−1, n) predetermined storage level has been determined, for maintaining said stored data at said ith (i=2, 3, . . . , n−1, n) predetermined logic level in the data storage portions storing the data of said ith (respectively, i=2, 3, . . . , n−1, n) predetermined logic level and corresponding to the memory cells in which it has been determined that said ith (respectively, i=2, 3, . . . , n−1, n) predetermined storage level has not been successfully written, and for maintaining said stored data at said first predetermined logic level in the data storage portions storing the data of said first predetermined logic level.    
     
     
       20. The device according to  claim 19 , wherein said actual written states of said memory cells corresponding to the data storage portions storing the data of said ith (i=2, 3, . . . , n−1, n) predetermined logic level are simultaneously determined. 
     
     
       21. The device according to  claim 19 , wherein said actual written states of said memory cells corresponding to the data storage portions storing the data of said second, third, . . . , (n−1)th and nth predetermined logic levels are simultaneously determined. 
     
     
       22. The device according to  claim 19 , wherein said data of said ith (i=2, 3, . . . , n−1, n) predetermined logic level stored in the data storage portions corresponding to the memory cells in which successful writing has been determined are simultaneously modified to the data of said first predetermined logic level. 
     
     
       23. The device according to  claim 19 , wherein said data of said second, third, . . . , (n−1)th and nth predetermined logic levels stored in the data storage portions corresponding to the memory cells in which successful writing has been determined are simultaneously modified to the data of said first predetermined logic level. 
     
     
       24. The device according to  claim 19 , further comprising a plurality of data write end detection circuits coupled to said data storage portions for simultaneously detecting whether or not all of said data storage portions store the data of said first predetermined logic level. 
     
     
       25. The device according to  claim 24 , wherein each of said data write end detection circuits is provided for each of said data storage portions. 
     
     
       26. The device according to  claim 25 , wherein said data write end detection circuits are coupled to at least one common output line, and said data write end detection circuits output a programming completion signal on said common output line when each data storage portion stores the data of said first predetermined logic level. 
     
     
       27. The device according to  claim 26 , wherein said applying, determining and modifying are continued until said data write end detection circuits output said programming completion signal. 
     
     
       28. The device according to  claim 19 , wherein said applying, determining and modifying are continued until each memory cell is sufficiently written. 
     
     
       29. The device according to  claim 19 , wherein said write voltages are simultaneously applied to said respective of said memory cells. 
     
     
       30. The device according to  claim 29 , wherein said write voltages defined by said data stored in said data storage portions and applied to said respective of said memory cells differ according to said data stored in said data storage portions. 
     
     
       31. The device according to  claim 19 , wherein said programming control circuits are arranged adjacent to said memory cell array. 
     
     
       32. The device according to  claim 19 , wherein each of said programming control circuits is connected to a respective one of said bit lines. 
     
     
       33. The device according to  claim 19 , wherein said programming control circuits include bit line voltage regulators for selectively changing voltages of said bit lines according to said data stored in said data storage portions. 
     
     
       34. The device according to  claim 33 , wherein said voltages of said bit lines are selectively and simultaneously changed by said bit line voltage regulators. 
     
     
       35. A multi-level non-volatile semiconductor memory device comprising:
 a semiconductor substrate;    a plurality of bit lines;    a plurality of word lines insulatively intersecting said bit lines;    a memory cell array comprising a plurality of memory cells coupled to said word lines and bit lines, each memory cell including a transistor with a charge storage portion and having written states of first, second, . . . , (n−1)th and nth (n≧3) predetermined storage levels;    a plurality of programming control circuits coupled to said memory cell array for storing data of first, second, . . . , (n−1)th, and nth predetermined logic levels in data storage portions which define write voltages to be applied to respective of said memory cells, said data being initially set to initial data which are loaded from at least one input line coupled to said data storage portions, for applying said write voltages to said respective of said memory cells according to the data stored in said data storage portions, for determining actual written states of said memory cells, for modifying stored data at said first predetermined logic level in the data storage portions storing the data of said first predetermined logic level, and for selectively modifying said stored data to the data of said first predetermined logic level in only data storage portions initially storing the initial data of said ith (i=2, 3, . . . , n−1, n) predetermined logic level and corresponding to the memory cells in which successful writing of said ith (respectively, i=2, 3, . . . , n−1, n) predetermined storage level has been determined, such that only memory cells which are not sufficiently written have write voltages applied thereto which achieve the written state predetermined by the initial data in the respective memory cell upon application of the write voltages to the respective memory cell.    
     
     
       36. The device according to  claim 35 , wherein said actual written states of said memory cells corresponding to the data storage portions storing the data of said ith (i=2, 3, . . . , n−1, n) predetermined logic level are simultaneously determined. 
     
     
       37. The device according to  claim 35 , wherein said actual written states of said memory cells corresponding to the data storage portions storing the data of said second, third, . . . , (n−1)th and nth predetermined logic levels are simultaneously determined. 
     
     
       38. The device according to  claim 35 , wherein said data of said ith (i=2, 3, . . . , n−1, n) predetermined logic level stored in the data storage portions corresponding to the memory cells in which successful writing has been determined are simultaneously and selectively modified to the data of said first predetermined logic level. 
     
     
       39. The device according to  claim 35 , wherein said data of said second, third, . . . , (n−1)th and nth predetermined logic levels stored in the data storage portions corresponding to the memory cells in which successful writing has been determined are simultaneously and selectively modified to the data of said first predetermining logic level. 
     
     
       40. The device according to  claim 35 , further comprising a plurality of data write end detection circuits coupled to said data storage portions for simultaneously detecting whether or not all of said data storage portions store the data of said first predetermined logic level. 
     
     
       41. The device according to  claim 40 , wherein each of said data write end detection circuits is provided for each of said data storage portions. 
     
     
       42. The device according to  claim 41 , wherein said data write end detection circuits are coupled to at least one common output line, and said data write end detection circuits output a programming completion signal on said common output line when each data storage portion stores the data of said first predetermined logic level. 
     
     
       43. The device according to  claim 42 , wherein said applying, determining and selective modifying are continued until said data write end detection circuits output said programming completion signal. 
     
     
       44. The device according to  claim 35 , wherein said applying, determining and selective modifying are continued until each memory cell is sufficiently written. 
     
     
       45. The device according to  claim 35 , wherein said write voltages are simultaneously applied to said respective of said memory cells. 
     
     
       46. The device according to  claim 45 , wherein said write voltages defined by said data stored in said data storage portions and applied to said respective of said memory cells differ according to said data stored in said data storage portions. 
     
     
       47. The device according to  claim 45 , wherein said programming control circuits are arranged adjacent to said memory cell array. 
     
     
       48. The device according to  claim 35 , wherein each of said programming control circuits is connected to a respective one of said bit lines. 
     
     
       49. The device according to  claim 35 , wherein said programming control circuits include bit line voltage regulators for selectively changing voltages of said bit lines according to said data stored in said data storage portions. 
     
     
       50. The device according to  claim 49 , wherein said voltages of said bit lines are selectively and simultaneously changed by said bit line voltage regulators. 
     
     
       51. A multi-level non-volatile semiconductor memory device comprising:
 a semiconductor substrate;    a plurality of bit lines;    a plurality of word lines insulatively intersecting said bit lines;    a memory cell array comprising a plurality of memory cells coupled to said word lines and bit lines, each memory cell including a transistor with a charge storage portion and having written states of first, second, . . . (n−1)th and nth (n≧3) predetermined storage levels;    a plurality of cell selection circuits coupled to said memory cell array for controlling selection of memory cells and application of write voltages to the selected memory cells;    a plurality of data circuits coupled to said memory cell array for storing write control data of first, second, . . . , (n−1)th, and nth predetermined logic levels which define write control voltages to be applied to respective of said memory cells selected by said cell selection circuits, said write control data being initially set to initial write control data which are loaded from at least one input line coupled to said data circuits, for applying said write control voltages to said respective of said memory cells, for selectively sensing actual written states of only those of said respective memory cells corresponding to the data circuits in which the write control data of said second, third, . . . , (n−1)th and nth predetermined logic levels are stored, for maintaining stored write control data at said first predetermined logic level in the data circuits storing the write control data of said first predetermined logic level, and for selectively modifying said stored write control data to the write control data of said first predetermined logic level in only data circuits initially storing the initial write control data of said ith (i=2, 3, . . . , n−1, n) predetermined logic level and corresponding to the memory cells in which successful writing of said ith (respectively, i=2, 3, . . . , n−1, n) predetermined storage level has been sensed, such that only memory cells which are not sufficiently written have write control voltages applied thereto which achieve the written state predetermined by the initial write control data in the respective memory cell upon application of the write control voltages to the respective memory cell.    
     
     
       52. The device according to  claim 51 , wherein said actual written states of said memory cells corresponding to the data circuits storing the write control data of said ith (i=2, 3, . . . , n−1, n) predetermined logic level are simultaneously sensed. 
     
     
       53. The device according to  claim 51 , wherein said actual written states of said memory cells corresponding to the data circuits storing the write control data of said second, third, . . . , (n−1)th and nth predetermined logic levels are simultaneously sensed. 
     
     
       54. The device according to  claim 51 , wherein said write control data of said ith (i=2, 3, . . . , n−1, n) predetermined logic level stored in the data circuits corresponding to the memory cells in which successful writing has been sensed are simultaneously and selectively modified to the write control data of said first predetermined logic level. 
     
     
       55. The device according to  claim 51 , wherein said write control data of said second, third, . . . (n−1)th and nth predetermined logic levels stored in the data circuits corresponding to the memory cells in which successful writing has been sensed are simultaneously and selectively modified to the write control data of said first predetermined logic level. 
     
     
       56. The device according to  claim 51 , further comprising a plurality of data write end detection circuits coupled to said data circuits for simultaneously detecting whether or not all of said data circuits store the write control data of said first predetermined logic level. 
     
     
       57. The device according to  claim 56 , wherein each of said data write end detection circuits is provided for each of said data circuits. 
     
     
       58. The device according to  claim 57 , wherein said data write end detection circuits are coupled to at least one common output line, and said data write end detection circuits output a programming completion signal on said common output line when each data circuit stores the write control data of said first predetermined logic level. 
     
     
       59. The device according to  claim 58 , wherein said applying, selective sensing and selective modifying are continued until said data write end detection circuits output said programming completion signal. 
     
     
       60. The device according to  claim 51 , wherein said applying, selective sensing and selective modifying are continued until each memory cell is sufficiently written. 
     
     
       61. The device according to  claim 51 , wherein said write control voltages are simultaneously applied to said respective of said memory cells. 
     
     
       62. The device according to  claim 61 , wherein said write control voltages defined by said write control data stored in said data circuits and applied to said respective of said memory cells differ according to said write control data stored in said data circuits. 
     
     
       63. The device according to  claim 51 , wherein said data circuits are arranged adjacent to said memory cell array. 
     
     
       64. The device according to  claim 51 , wherein each of said data circuits is connected to a respective one of said bit lines. 
     
     
       65. The device according to  claim 51 , wherein said data circuits include bit line voltage regulators for selectively changing voltages of said bit lines according to said write control data stored in said data circuits. 
     
     
       66. The device according to  claim 65 , wherein said voltages of said bit lines are selectively and simultaneously changed by said bit line voltage regulators. 
     
     
       67. A multi-level non-volatile semiconductor memory device comprising:
 a semiconductor substrate;    a plurality of bit lines;    a plurality of word lines insulatively intersecting said bit lines;    a memory cell array comprising a plurality of memory cells coupled to said word lines and bit lines, each memory cell including a transistor with a charge storage portion and having written states of first, second, . . . , (n−1)th and nth (n≧3) predetermined storage levels;    a plurality of cell selection circuits coupled to said memory cell array for controlling selection of memory cells and application of write voltages to the selected memory cells;    a plurality of data circuits coupled to said memory cell array for storing write control data of first, second, . . . , (n−1)th, and nth predetermined logic levels which define write control voltages to be applied to respective of said memory cells selected by said cell selection circuits, for applying said write control voltages to said respective of said memory cells, for selectively sensing actual written states of only those of said respective memory cells corresponding to the data circuits in which the write control data of said second, third, . . . , (n−1)th and nth predetermined logic levels are stored, for modifying stored write control data from said ith (i=2, 3, . . . , n−1, n) predetermined logic level to said first predetermined logic level in the data circuits storing the write control data of said ith (respectively, i=2, 3, . . . , n−1, n) predetermined logic level and corresponding to the memory cells in which successful writing of said ith (respectively, i=2, 3, . . . , n−1, n) predetermined storage level has been sensed, for maintaining said stored write control data at said ith (i=2, 3, . . . , n−1, n) predetermined logic level in the data circuits storing the write control data of said ith (respectively, i=2, 3, . . . , n−1, n) predetermined logic level and corresponding to the memory cells in which it has been sensed that said ith (respectively, i=2, 3, . . . , n−1, n) predetermined storage level has not been successfully written, and for maintaining said stored write control data at said first predetermined logic level in the data circuits storing the write control data of said first predetermined logic level.    
     
     
       68. The device according to  claim 67 , wherein said write control data stored in said data circuits are initially set to initial write control data, and then said initial write control data stored in said data circuits are modified. 
     
     
       69. The device according to  claim 68 , wherein said initial write control data are loaded from at least one input line coupled to said data circuits. 
     
     
       70. The device according to  claim 67 , wherein said actual written states of said memory cells corresponding to the data circuits storing the write control data of said ith (i=2, 3, . . . , n−1, n) predetermined logic level are simultaneously sensed. 
     
     
       71. The device according to  claim 67 , wherein said actual written states of said memory cells corresponding to the data circuits storing the write control data of said second, third, . . . , (n−1)th and nth predetermined logic levels are simultaneously sensed. 
     
     
       72. The device according to  claim 67 , wherein said write control data of said ith (i=2, 3, . . . , n−1, n) predetermined logic level stored in the data circuits corresponding to the memory cells in which successful writing has been sensed are simultaneously modified to the write control data of said first predetermined logic level. 
     
     
       73. The device according to  claim 67 , wherein said write control data of said second, third, . . . , (n−1)th and nth predetermined logic levels stored in the data circuits corresponding to the memory cells in which successful writing has been sensed are simultaneously modified to the write control data of said first predetermined logic level. 
     
     
       74. The device according to  claim 67 , further comprising a plurality of data write end detection circuits coupled to said data circuits for simultaneously detecting whether or not all of said data circuits store the write control data of said first predetermined logic level. 
     
     
       75. The device according to  claim 74 , wherein each of said data write end detection circuits is provided for each of said data circuits. 
     
     
       76. The device according to  claim 75 , wherein said data write end detection circuits are coupled to at least one common output line, and said data write end detection circuits output a programming completion signal on said common output line when each data circuit stores the write control data of said first predetermined logic level. 
     
     
       77. The device according to  claim 76 , wherein said applying, selective sensing and modifying are continued until said data write end detection circuits output said programming completion signal. 
     
     
       78. The device according to  claim 67 , wherein said applying, selective sensing and modifying are continued until each memory cell is sufficiently written. 
     
     
       79. The device according to  claim 67 , wherein said write control voltages are simultaneously applied to said respective of said memory cells. 
     
     
       80. The device according to  claim 79 , wherein said write control voltages defined by said write control data stored in said data circuits and applied to said respective of said memory cells differ according to said write control data stored in said data circuits. 
     
     
       81. The device according to  claim 67 , wherein said data circuits are arranged adjacent to said memory cell array. 
     
     
       82. The device according to  claim 67 , wherein each of said data circuits is connected to a respective one of said bit lines. 
     
     
       83. The device according to  claim 67 , wherein said data circuits include bit line voltage regulators for selectively changing voltages of said bit lines according to said write control data stored in said data circuits. 
     
     
       84. The device according to  claim 83 , wherein said voltages of said bit lines are selectively and simultaneously changed by said bit line voltage regulators. 
     
     
       85. A multi-level non-volatile semiconductor memory device comprising:
 a semiconductor substrate;    a plurality of bit lines;    a plurality of word lines insulatively intersecting said bit lines;    a memory cell array comprising a plurality of memory cells coupled to said word lines or bit lines, each memory cell including a transistor with a charge storage portion and having written states of first, second, . . . , (n−1)th and nth (n≧3) predetermined storage levels;    a plurality of cell selection circuits coupled to said memory cell array for controlling selection of memory cells and application of write voltages to the selected memory cells;    a plurality of data circuits coupled to said memory cell array for storing write control data of first, second, . . . (n−1)th, and nth predetermined logic levels which define write control voltages to be applied to respective of said memory cells selected by said cell selection circuits, for applying said write control voltages to said respective of said memory cells, for sensing actual written states of only those of said respective memory cells corresponding to the data circuits in which the write control data of said second, third, . . . , (n−1)th and nth predetermined logic levels are stored, for modifying stored write control data from said ith (i=2, 3, . . . , n−1, n) predetermined logic level to said first predetermined logic level in the data circuits storing the write control data of said ith (respectively, i=2, 3, . . . , n−1, n) predetermined logic level and corresponding to the memory cells in which successful writing of said ith (respectively, i=2, 3, . . . , n−1, n) predetermined storage level has been sensed, for maintaining said stored write control data at said ith (i=2, 3, . . . , n−1, n) predetermined logic level in the data circuits storing the write control data of said ith (respectively, i=2, 3, . . . , n−1, n) predetermined logic level and corresponding to the memory cells in which it has been sensed that said ith (respectively, i=2, 3, . . . , n−1, n) predetermined storage level has not been successfully written, and for maintaining said stored write control data at said first predetermined logic level in the data circuits storing the write control data of said first predetermined logic level;    wherein results of said sensing of said actual written states by the data circuits storing the write control data of said ith (i=2, 3, . . . , n−1, n) predetermined logic level are determined on the basis of only whether or not the written state of the respective memory cell is said ith (respectively, i=2, 3, . . . , n−1, n) predetermined storage level.    
     
     
       86. The device according to  claim 85 , wherein said write control data stored in said data circuits are initially set to initial write control data, and then said initial write control data stored in said data circuits are modified. 
     
     
       87. The device according to  claim 85 , wherein said initial write control data are loaded from at least one input line coupled to said data circuits. 
     
     
       88. The device according to  claim 85 , wherein said actual written states of said memory cells corresponding to the data circuits storing the write control data of said ith (i=2, 3, . . . , n−1, n) predetermined logic level are simultaneously sensed. 
     
     
       89. The device according to  claim 85 , wherein said actual written states of said memory cells corresponding to the data circuits storing the write control data of said second, third, . . . , (n−1)th and nth predetermined logic levels are simultaneously sensed. 
     
     
       90. The device according to  claim 85 , wherein said write control data of said ith (i=2, 3, . . . , n−1, n) predetermined logic level stored in the data circuits corresponding to the memory cells in which successful writing has been sensed are simultaneously modified to the write control data of said first predetermined logic level. 
     
     
       91. The device according to  claim 85 , wherein said write control data of said second, third, . . . , (n−1)th and nth predetermined logic levels stored in the data circuits corresponding to the memory cells in which successful writing has been sensed are simultaneously modified to the write control data of said first predetermined logic level. 
     
     
       92. The device according to  claim 85 , further comprising a plurality of data write end detection circuits coupled to said data circuits for simultaneously detecting whether or not all of said data circuits store the write control data of said first predetermined logic level. 
     
     
       93. The device according to  claim 92 , wherein each of said data write end detection circuits is provided for each of said data circuits. 
     
     
       94. The device according to  claim 93 , wherein said data write end detection circuits are coupled to at least one common output line, and said data write end detection circuits output a programming completion signal on said common output line when each data circuit stores the write control data of said first predetermined logic level. 
     
     
       95. The device according to  claim 94 , wherein said applying, sensing and modifying are continued until said data write end detection circuits output said programming completion signal. 
     
     
       96. The device according to  claim 85 , wherein said applying, sensing and modifying are continued until each memory cell is sufficiently written. 
     
     
       97. The device according to  claim 85 , wherein said write control voltages are simultaneously applied to said respective of said memory cells. 
     
     
       98. The device according to  claim 97 , wherein said write control voltages defined by said write control data stored in said data circuits and applied to said respective of said memory cells differ according to said write control data stored in said data circuits. 
     
     
       99. The device according to  claim 85 , wherein said data circuits are arranged adjacent to said memory cell array. 
     
     
       100. The device according to  claim 85 , wherein each of said data circuits is connected to a respective one of said bit lines. 
     
     
       101. The device according to  claim 85 , wherein said data circuits include bit line voltage regulators for selectively changing voltages of said bit lines according to said write control data stored in said data circuits. 
     
     
       102. The device according to  claim 101 , wherein said voltages of said bit lines are selectively and simultaneously changed by said bit line voltage regulators. 
     
     
       103. The device according to  claim 85 , wherein each of said results is stored in the respective data circuit and used at latest write control data. 
     
     
       104. A multi-level non-volatile semiconductor memory device comprising:
 a semiconductor substrate;    a plurality of bit lines;    a plurality of word lines insulatively intersecting said bit lines;    a memory cell array comprising a plurality of memory cells coupled to said word lines and bit lines, each memory cell including a transistor with a charge storage portion and having written states of first, second, . . . , (n−1)th and nth (n≧3) predetermined storage levels;    a plurality of cell selection circuits coupled to said memory cell array for controlling selection of memory cells and application of write voltages to the selected memory cells;    a plurality of data circuits coupled to said memory cell array for storing write control data of first, second, . . . , (n−1)th, and nth predetermined logic levels which define write control voltages to be applied to respective of said memory cells selected by said cell selection circuits, for applying said write control voltages to said respective of said memory cells, for sensing actual written states of only those of said respective memory cells corresponding to the data circuits in which the write control data of said second, third, . . . , (n−1)th and nth predetermined logic levels are stored, for modifying stored write control data from said ith (i=2, 3, . . . , n−1, n) predetermined logic level to said first predetermined logic level in the data circuits storing the write control data of said ith (respectively, i=2, 3, . . . , n−1, n) predetermined logic level and corresponding to the memory cells in which successful writing of said ith (respectively, i=2, 3, . . . , n−1, n) predetermined storage level has been sensed, for maintaining said stored write control data at said ith (i=2, 3, . . . , n−1, n) predetermined logic level in the data circuits storing the write control data of said ith (respectively, i=2, 3, . . . , n−1, n) predetermined logic level and corresponding to the memory cells in which it has been sensed that said ith (respectively, i=2, 3, . . . , n−1, n) predetermined storage level has not been successfully written, and for maintaining said stored write control data at said first predetermined logic level in the data circuits storing the write control data of said first predetermined logic level,    wherein with respect to said sensing of said actual written states, the data circuits storing the write control data of said ith (i=2, 3, . . . , n−1, n) predetermined logic level sense only whether or not the written state of the respectively memory cell in said ith ((respectively, i=2, 3, n−1, n) predetermined storage level.    
     
     
       105. The device according to  claim 104 , wherein said write control data stored in said data circuits are initially set to initial write control data, and then said initial write control data stored in said data circuits are modified. 
     
     
       106. The device according to  claim 105 , wherein said initial write control data are loaded from at least one input line coupled to said data circuits. 
     
     
       107. The device according to  claim 104 , wherein each of said data circuits is connected to a respective one of said bit lines, and the data circuits storing the write control data of said ith (i=2, 3, . . . , n−1, n) predetermined logic level sense voltage levels of the respective bit lines by comparing with ith (respectively, i=2, 3 . . . , n−1, n) reference voltage. 
     
     
       108. The device according to  claim 104 , wherein said actual written states of said memory cells corresponding to the data circuits storing the write control data of said ith (i=2, 3, . . . , n−1, n) predetermined logic level are simultaneously sensed. 
     
     
       109. The device according to  claim 104 , wherein said actual written states of said memory cells corresponding to the data circuits storing the write control data of said second, third, . . . , (n−1)th and nth predetermined logic levels are simultaneously sensed. 
     
     
       110. The device according to  claim 104 , wherein said write control data of said ith (i=2, 3, . . . , n−1, n) predetermined logic level stored in the data circuits corresponding to the memory cells in which successful writing has been sensed are simultaneously modified to the write control data of said first predetermined logic level. 
     
     
       111. The device according to  claim 104 , wherein said write control data of said second, third, . . . , (n−1)th and nth predetermined logic levels stored in the data circuits corresponding to the memory cells in which successful writing has been sensed are simultaneously modified to the write control data of said first predetermined logic level. 
     
     
       112. The device according to  claim 104 , wherein said applying, sensing and modifying are continued until each memory cell is sufficiently written. 
     
     
       113. The device according to  claim 104 , wherein said write control voltages are simultaneously applied to said respective of said memory cells. 
     
     
       114. The device according to  claim 113 , wherein said write control voltages defined said write control data stored in said data circuits and applied to said respective of said memory cells differ according to said write control data stored in said data circuits. 
     
     
       115. The device according to  claim 104 , wherein said data circuits are arranged adjacent to said memory cell array. 
     
     
       116. The device according to  claim 104 , wherein each of said data circuits is connected to a respective one of said bit lines. 
     
     
       117. The device according to  claim 104 , wherein said data circuits include bit line voltage regulators for selectively charging voltages of said bit lines according to said write control data stored in said data circuits. 
     
     
       118. The device according to  claim 117 , wherein said voltages of said bit lines are selectively and simultaneously changed by said bit line voltage regulators. 
     
     
       119. The device according to  claim 104 , wherein each of results of said sensing is stored in the respective data circuit and used at latest write control data. 
     
     
       120. A multi- level nonvolatile semiconductor memory device comprising:      a NAND - cell unit including a plurality of memory cells connected in series, each of said memory cells including a transistor with a control gate and a charge storage portion and having multi - level storage states;        a plurality of word lines connected to respective control gates;        a bit line coupled to one end of said NAND - cell unit;        a word line selector coupled to said word lines for selecting the word line of selected memory cell;        a data latch circuit coupled to said bit line for storing data, said data latch circuit including at least two binary data latch circuits;        a first bit line bias circuit coupled to said bit line for biasing said bit line dependently on the data stored in said data latch circuit; and        a second bit line bias circuit coupled to said bit line for biasing said bit line independently of the data stored in said data latch circuit.