Thin film transistor substrate

Abstract

A TFT substrate includes a gate electrode and gate pad on a transparent substrate, an insulating layer on the gate electrode and exposing a portion of the gate pad, a semiconductor film on the insulating layer and the gate electrode, an impurity doped semiconductor film on the semiconductor film, the impurity doped semiconductor film contacting a top surface of the semiconductor film over the gate electrode, source and drain electrodes and a data line on a portion of the impurity doped semiconductor film, a protection film on the source and drain electrodes and the insulating layer in a gate pad area, the protection film having a contact hole over the drain electrode exposing a top surface of the gate pad, a first pixel electrode electrically connected to the drain electrode on the protection film, and a second pixel electrode directly connected to the exposed top surface of the gate pad.

1. A TFT substrate, comprising:
 a gate electrode, a gate pad and a gate line formed on a transparent substrate and comprising a first wire pattern containing Al formed over the transparent substrate, and a second wire pattern containing a refractory metal formed over the first wire pattern;  
 an insulating layer pattern formed over the gate electrode and exposing a portion of the second wire pattern of the gate pad containing the refractory metal;  
 a semiconductor film pattern formed over the insulating layer pattern and over the gate electrode;  
 an impurity doped semiconductor film pattern formed on the semiconductor film pattern, wherein entire bottom surfaces of the impurity doped semiconductor film pattern contacts  contact a top surface of the semiconductor film pattern formed over the gate electrode;  
 a source electrode,  connected to a data line, and a drain electrode, and a data line  formed over a portion  portions of the impurity doped semiconductor film pattern;  
 a protection film pattern formed over the source electrode and the drain electrode and over the insulating layer pattern in an area of the gate pad, the protection film pattern having a contact hole over the drain electrode and exposing a top surface of the gate pad;  
 a first pixel electrode pattern electrically connected to the drain electrode on the protection film pattern; and  
 a second pixel electrode pattern directly connected to the exposed top surface of the second wire pattern of the gate pad containing the refractory metal,  
   wherein the semiconductor film pattern includes a portion disposed between the source electrode and the drain electrode, and wherein a portion of the protection film pattern directly contacts a top surface of the portion of the semiconductor film pattern disposed between the source electrode and the drain electrode, and    
   wherein an interior angle formed between a lateral surface of the first wire pattern containing Al and the transparent substrate is smaller than an interior angle formed between a lateral surface of the second wire pattern containing the refractory metal and the transparent substrate .  
 
     
     
       2. A TFT substrate as recited in  claim 1 , wherein the gate electrode, the gate pad and the gate line comprise a metal film pattern and wherein a width of the metal film pattern becomes narrower from the bottom of the metal film pattern. 
     
     
       3. A TFT substrate as recited in  claim 1 , wherein a portion of the protection film pattern directly contacts the semiconductor film pattern located between the source electrode and the drain electrode. 
     
     
       4. A TFT substrate as recited in  claim 1 , wherein the insulating layer pattern comprises a nitride film of the formula SiNx. 
     
     
       5. A TFT substrate, comprising:
 a gate electrode, a gate pad and a gate line which form a metal film pattern, wherein a width of the metal film pattern becomes narrower from a bottom of the metal film pattern and the metal film pattern comprises a first wire pattern containing Al, and a second wire pattern containing Mo formed over the first wire pattern;  
 an insulating layer pattern formed over the gate electrode and exposing a portion of the second wire pattern of the gate pad containing Mo;  
 a semiconductor film pattern formed over the insulating layer pattern and over the gate electrode;  
 an impurity doped semiconductor film pattern formed on the semiconductor film pattern, wherein entire bottom surfaces of the impurity doped semiconductor film pattern contacts  contact a top surface of the semiconductor film pattern formed over the gate electrode;  
 a source electrode,  connected to a data line, and a drain electrode, and a data line  formed over a portion  portions of the impurity doped semiconductor film pattern;  
 a protection film pattern formed over the source electrode and the drain electrode and over the insulating layer pattern in an area of the gate pad, the protection film pattern having a contact hole over the drain electrode and exposing a top surface of the gate pad;  
 a first pixel electrode pattern electrically connected to the drain electrode on the protection film pattern; and  
 a second pixel electrode pattern electrically connected to the exposed area  top surface of the second wire pattern of the gate pad containing Mo,  
   wherein the second wire pattern containing Mo has a portion that protrudes beyond and overhangs an edge of an upper surface of the first wire pattern containing Al .  
 
     
     
       6. A TFT substrate as recited in  claim 5 , wherein a portion of the protection film pattern directly contacts the semiconductor film pattern located  disposed between the source electrode and the drain electrode. 
     
     
       7. A TFT substrate as recited in  claim 5 , wherein the insulating layer pattern comprises a nitride film of the formula SiNx. 
     
     
       8. A TFT substrate, comprising:
   a gate electrode, a gate pad and a gate line formed on a transparent substrate;        an insulating layer pattern formed over the gate electrode and exposing a portion of the gate pad;        a semiconductor film pattern formed over the insulating layer pattern and over the gate electrode;        an impurity doped semiconductor film pattern formed on the semiconductor film pattern, wherein entire bottom surfaces of the impurity doped semiconductor film pattern contact a top surface of the semiconductor film pattern formed over the gate electrode;        a source electrode connected to a data line, and a drain electrode, which are formed over portions of the impurity doped semiconductor film pattern;        a protection film pattern formed over the source electrode and the drain electrode and over the insulating layer pattern in an area of the gate pad, the protection film pattern having a contact hole over the drain electrode and exposing a top surface of the gate pad;        a first pixel electrode pattern electrically connected to the drain electrode on the protection film pattern; and        a second pixel electrode pattern directly connected to the exposed top surface of the gate pad,        wherein the gate electrode, the gate pad and the gate line comprise a first metal film pattern formed over the transparent substrate and a second metal film pattern formed over the first metal film pattern and the second pixel electrode pattern is directly connected to the second metal film pattern, and        wherein an inside angle formed between a lateral surface of the first metal film pattern and the transparent substrate is smaller than an inside angle formed between a lateral surface of the second metal film pattern and the transparent substrate.     
     
     
       9. A TFT substrate as recited in  claim 8 , wherein the second metal film pattern comprises a metal selected from the group consisting of Cr, Mo, Ta and Ti. 
     
     
       10. A TFT substrate as recited in  claim 9 , wherein the first metal film pattern comprises Al or an Al- alloy.   
     
     
       11. A TFT substrate as recited in  claim 1 , wherein the second wire pattern containing the refractory metal has a portion that protrudes beyond and overhangs an edge of an upper surface of the first wire pattern containing Al. 
     
     
       12. A TFT substrate as recited in  claim 11 , wherein a thickness of the first wire pattern containing Al is  2 , 000 - 4000  Å. 
     
     
       13. A TFT substrate as recited in  claim 1 , wherein the insulating layer pattern comprises a nitride film and the protection film pattern is comprised of an insulating material different from the nitride film of the insulating layer pattern. 
     
     
       14. A TFT substrate as recited in  claim 1 , wherein the insulating layer pattern comprises a nitride film and a thickness of the protection film pattern is less than a thickness of the insulating layer pattern. 
     
     
       15. A TFT substrate as recited in  claim 14 , wherein the thickness of the protection film pattern is  1 , 000 - 3 , 000  Å and the thickness of the insulating layer pattern is more than  3000  Å. 
     
     
       16. A TFT substrate as recited in  claim 10 , wherein a thickness of the second metal film pattern is the same or less than that of the first metal film pattern. 
     
     
       17. A TFT substrate as recited in  claim 8 , wherein a width of the second metal film is the same or less than that of the upper surface of the first metal film pattern. 
     
     
       18. A TFT substrate as recited in  claim 8 , wherein the second metal film pattern has a portion that protrudes beyond and overhangs an edge of an upper surface of the first metal film pattern. 
     
     
       19. A TFT substrate as recited in  claim 8 , wherein the insulating layer pattern comprises a nitride film and the protection film pattern is comprised of an insulating material different from the nitride film of the insulating layer pattern. 
     
     
       20. A TFT substrate as recited in  claim 5 , wherein an interior angle formed between a lateral surface of the first wire pattern containing Al and the transparent substrate, is smaller than an interior angle formed between a lateral surface of the second wire pattern containing Mo and the transparent substrate. 
     
     
       21. A TFT substrate as recited in  claim 20 , wherein a thickness of the first wire pattern containing Al is  2 , 000 - 4 , 000  Å. 
     
     
       22. A TFT substrate as recited in  claim 21 , wherein the insulating layer pattern comprises a nitride film and the protection film pattern is comprised of an insulating material different from the nitride film of the insulating layer pattern. 
     
     
       23. A TFT substrate as recited in  claim 20 , wherein the insulating layer pattern comprises a nitride film and a thickness of the protection film pattern is less than a thickness of the insulating layer pattern. 
     
     
       24. A TFT substrate as recited in  claim 23 , wherein the thickness of the protection film pattern is  1 , 000 - 3 , 000  Å and the thickness of the insulating layer pattern is more than  3000  Å.