Extended cardbus/PC card controller with split-bridge technology

Abstract

An improved extended cardbus/PC card controller ( 20 ) incorporating proprietary Split-Bridge™ high speed serial communication technology for interconnecting a conventional parallel system bus via a high speed serial link with a remote peripheral device. The extend cardbus/PC card controller is adapted to interface the parallel system bus, which may be PCI, PCMCIA, integrated, or some other parallel I/O bus architecture, with peripheral devices via PC cards, and now optionally via a high speed serial link using the proprietary serial Split-Bridge™ technology. The serial Split-Bridge™ technology provides real time interconnection between the parallel system bus and the remote device which may also be based on a parallel system data bus architecture, over a serial link, which serial link appears to be transparent between the buses and thus facilitates high speed data transfer exceeding data rates of 1.0 GigaHertz.

1. An interface comprising:
 first electronics adapted to interface parallel data from a parallel data bus to a first bus; and  
 second electronics adapted  configured to interface said parallel data from said parallel data bus into serial data adapted  and configured to interface with a second remote bus, said second electronics configured to converting  said parallel data into said serial data and, without inserting bus wait states, send said serial data to said second remote bus without requiring any external signal from said second remote bus.  
 
     
     
       2. The interface as specified in  claim 1  wherein said second electronics comprises Split-Bridge™  split-bridge serial interface electronics. 
     
     
       3. The interface as specified in  claim 1  wherein said parallel data bus is based on PCI-type or PCMCIA-type interface standards. 
     
     
       4. The interface as specified in  claim 1  wherein said serial data has a serial data rate exceeding 1.0 Giga bits/second. 
     
     
       5. The interface as specified in  claim 1  wherein said first electronics comprises a digital signal processor (DSP). 
     
     
       6. The interface card as specified in  claim 1  wherein said first electronics comprises Cardbus electronics. 
     
     
       7. The interface card as specified in  claim 1  wherein said first electronics and said second electronics are adapted to concurrently  support transfer of data to said respective  first bus and said second buses  remote bus, respectively. 
     
     
       8. A method of interfacing parallel data on a parallel system bus to a first bus and a second remote bus, comprising the steps of:
 a) converting a first portion of the parallel data on the parallel system bus to parallel data adapted to communicate with said first bus; and  
 b) converting a second portion of the parallel data on the parallel system bus to high-speed serial data, which said serial data is sent, without inserting bus wait states, to the second remote bus without requiring or receiving a signal from said second remote bus before sending said serial data.  
 
     
     
       9. The method as specified in  claim 8  further comprising the step of using a Split-Bridge™  split-bridge serial interface. 
     
     
       10. The method as specified in  claim 8  wherein said parallel system bus is based on PCI-type or Cardbus-type bus standard. 
     
     
       11. The method as specified in  claim 8  wherein said serial data is sent at a data rate exceeding 1.0 GHZ. 
     
     
       12. The method as specified in  claim 8  wherein said step a) and said step b) are performed in a single electronic device. 
     
     
       13. The method as specified in  claim 12  wherein said electronic device comprises a Digital Signal Processor (DSP). 
     
     
       14. The method as specified in  claim 8  wherein a retry message is sent in advance of sending said serial data. 
     
     
       15. The method as specified in  claim 8  wherein said step a) uses Cardbus electronics. 
     
     
       16. An interface comprising:
 first electronics adapted to interface parallel data from a parallel data bus to a first bus; and    second electronics configured to interface said parallel data from said parallel data bus into serial data and configured to interface with a second remote bus, said second electronics configured to convert said parallel data into said serial data and, without additional bus wait states, send said serial data to said second remote bus, said second electronics configured to add tag data indicative of a transaction type to the serial data.   
     
     
       17. The interface as specified in  claim 16  wherein said second electronics comprises split-bridge serial interface electronics. 
     
     
       18. The interface as specified in  claim 16  wherein said parallel data bus is based on PCI-type or PCMCIA-type interface standards. 
     
     
       19. The interface as specified in  claim 16  wherein said serial data has a serial data rate exceeding  1 . 0  Giga bits/second. 
     
     
       20. The interface as specified in  claim 16  wherein said first electronics comprises a digital signal processor (DSP). 
     
     
       21. The interface card as specified in  claim 16  wherein said first electronics comprises Cardbus electronics. 
     
     
       22. The interface card as specified in  claim 16  wherein said first electronics and said second electronics are adapted to support transfer of data to said first bus and said second remote bus, respectively. 
     
     
       23. A method of interfacing parallel data on a parallel system bus to a first bus and a second remote bus, comprising:
 a) converting a first portion of the parallel data on the parallel system bus to parallel data adapted to communicate with said first bus; and    b) converting a second portion of the parallel data on the parallel system bus to high-speed serial data, which said serial data is sent, without requiring bus wait states, to the second remote bus, said serial data including a tag indicative of a transaction type.   
     
     
       24. The method as specified in  claim 23  further comprising the step of using a split-bridge serial interface. 
     
     
       25. The method as specified in  claim 23  wherein said parallel system bus is based on PCI or Cardbus bus standard. 
     
     
       26. The method as specified in  claim 23  wherein said serial data is sent at a data rate exceeding  1 . 0  GHZ. 
     
     
       27. The method as specified in  claim 23  wherein said step a) and said step b) are performed in a single electronic device. 
     
     
       28. The method as specified in  claim 27  wherein said electronic device comprises a Digital Signal Processor (DSP). 
     
     
       29. The method as specified in  claim 23  wherein a retry message is sent in advance of sending said serial data. 
     
     
       30. The method as specified in  claim 23  wherein said step a) uses Cardbus electronics. 
     
     
       31. An interface, comprising:
 first electronics configured to interface parallel data from a parallel data bus to a first bus; and    second electronics configured to interface said parallel data from said parallel data bus into serial data and configured to interface with a second remote bus, said second electronics configured to add tag data indicative of a transaction type to the serial data.   
     
     
       32. The interface as specified in  claim 31  wherein said parallel data bus is based on PCI standard. 
     
     
       33. The interface as specified in  claim 31  wherein said second electronics further comprises a data register configured to store said parallel data. 
     
     
       34. The interface as specified in  claim 33  wherein said second electronics is configured to mirror said data register parallel data to a register of another remote said interface. 
     
     
       35. The interface as specified in  claim 31  wherein said second electronics is configured to add said tag data during a transaction. 
     
     
       36. The interface as specified in  claim 35  wherein the second electronics is configured to proceed to a data cycle without delay.