Boundary-scan input circuit for a reset pin

Abstract

A boundary-scan circuit method and apparatus for asserting an internal reset signal connected to core logic circuits of an electronic device in order to assure that testing will begin and end in a safe, known logic state. A safe end state is assured even if the system reset signal on an input pin of the electronic device is logically disconnected from the internal reset connection to the core logic, as often occurs in boundary-scan and related testing.

1. A circuit apparatus providing a reset signal to core logic of an electronic device, said circuit apparatus comprising:
 storage means for storing and outputting a reset control signal;  
 means for logically combining said reset control signal and a built- in - self - test  (BIST) control signal into a reset-and-BIST control signal at an output thereof; and  
 means for controllably switching either a first input that is connected to  receives a system reset signal or a second input that is connected to said output of said logically combining means to an output thereof  of said switching means under control of a normal-or-test signal that is connected  propagated to a control input of said logically combining means; and  
 said output of said controllably  switching means is connected to said core logic and provides said reset signal.  
 
     
     
       2. A circuit apparatus providing a reset signal to core logic of an electronic device, according to  claim 1 , wherein said storage means is a transparent latch. 
     
     
       3. A circuit apparatus providing a reset signal to core logic of an electronic device, according to  claim 2 , wherein said logically combining means is an OR gate having a plurality of inverting inputs and a non-inverting output. 
     
     
       4. A circuit apparatus providing a reset signal to core logic of an electronic device, according to  claim 3 , wherein said controllably switching means is a 2-to-1 multiplexer. 
     
     
       5. A circuit apparatus providing a reset signal to core logic of an electronic device, according to  claim 4 , wherein said transparent latch is resettable. 
     
     
       6. A circuit apparatus providing a reset signal to core logic of an electronic device, according to  claim 5 , wherein said  an output of said transparent latch is an inverting output. 
     
     
       7. A circuit apparatus providing a reset signal to core logic of an electronic device, according to  claim 1 , further comprising second means for logically combining said reset signal output from said output of said controllably switching means and an external test control signal. 
     
     
       8. A circuit apparatus providing a reset signal to core logic of an electronic device, according to  claim 7 , wherein said second logically combining means is an OR gate, said OR gate having a plurality of inverting inputs and an inverted output. 
     
     
       9. An input circuit connected to a reset pin of a  an electronic device, comprising:
 boundary-scan register means for storing a boundary-scan test information bit;  
 said boundary-scan register means having an inverted output of the logic level stored therein;  
 a logical sum means for taking a logical sum of a first inverting input that is connected to said boundary-scan register means inverted output and a second inverting input that is connected to  receives a built- in - self - test  (BIST) control signal and providing a result at an output thereof;  
 a first 2-to-1 multiplexer having one data input connected to said output of said logical sum means, another data input connected to the  an input reset pin, a select input connected to a normal/test pin, and an output that is multiplexed to one of said data inputs under the control of a select signal upon said select  normal/test pin;  
 a second logical sum means having a first inverting input connected to said first 2-to-1 multiplexer output and a second inverting input connected through an inverter to an external-test control signal, wherein said second logical sum means is for taking a logical sum of the inverses of the logic signals on it  its two inputs and inverting the logic sum thereof to provide a reset signal to core logic connected at an output of said second logical sum means;  
 whereby if said external-test control signal is at a logic low level, said reset signal to said core logic is active such that said core logic is held reset as long as said external test control signal is not  at a logic level other than said logic low level.  
 
     
     
       10. An input circuit connected to a system reset signal  a reset pin of an electronic device as set forth in  claim 9 , further comprising:
 a second 2-to-1 multiplexer included as part of said boundary-scan register means having one of its data inputs connected to a serial data input, its other data input connected to said output of said first 2-to-1 multiplexer and a select input connected to a shift select control signal whereby said shift control signal selects either the serial data input signal or the output signal of the first 2-to-1 multiplexer as a logic level to be stored in said boundary-scan register means.  
 
     
     
       11. An input circuit connected to a system reset signal  a reset pin of a electronic device as set forth in  claim 9 , wherein if said output of said first 2-to-1 multiplexer is at a logic low level, said reset signal to said core logic is active such that said core logic is held reset as long as said first 2-to-1 multiplexer output is at a logic low level. 
     
     
       12. An input circuit connected to a system reset signal  a reset pin of an electronic device as set forth in  claim 11  wherein said boundary-scan register means has an asynchronous reset input that causes said inverted output of said boundary-scan register means to be a logic high signal if said asynchronous input is driven to a logic low level. 
     
     
       13. An input circuit connected to a system reset signal  a reset pin of an electronic device as set forth in  claim 9 , wherein said boundary-scan register means includes a type D flip-flop and a latch with a data input of said latch being connected to a non-inverted output of said type D flip-flop. 
     
     
       14. An input circuit connected to a system reset signal  a reset pin of an electronic device as set forth in  claim 9 , wherein said first logical sum means is an OR gate having inverting inputs and said second logical sum means is an OR gate having inverting inputs and an inverted output. 
     
     
       15. A method for resetting core logic circuits connected to a boundary-scan input circuit in an electronic device comprising the steps of:
 asserting a reset signal that resets a boundary-scan register that has an inverted output that is thereby driven to a logic high level;  
 inverting and logically summing said logic high level output from said boundary-scan register as one input and a built- in - self - test  (BIST) control signal as another input to provide a logic low level output;  
 multiplexing said logic level low output from said inverting and summing step by means of a multiplexer to provide a logic low level output of said multiplexer; and  
 inverting and logically summing said logic low level output from said multiplexer as one input and an external test control signal as another input to provide an internal logic high level and inverting said internal logic high level to a logic low level for resetting core logic of said electronic device.  
 
     
     
       16. A method for resetting core logic circuits connected to boundary-scan input circuit in an electronic device according to  claim 15  further comprising the steps of:
 asserting the reset signal that resets a boundary-scan register that has an inverted output that is thereby driven to a logic high level;  
 negating the BIST control signal if a BIST test is completed;  
 inverting and logically summing said logic high level output from said boundary-scan register as one input and a BIST control signal as another input to provide a logic low level output;  
 multiplexing said logic level low output from said inverting and summing step by means of a multiplexer to provide a logic low level output of said multiplexer;  
 inverting and logically summing said logic low level output from said multiplexer as one input and an external test control signal as another input to provide an internal logic high level and inverting said internal logic high level to a logic low level for resetting core logic of said electronic device; and  
 multiplexing a logic level from a system reset pin of the electronic device to resume normal operation after said BIST test is completed.  
 
     
     
       17. An electronic device, comprising:
   a circuit apparatus providing a reset signal to core logic of the electronic device, said circuit apparatus comprising:        storage means for storing and outputting a reset control signal;        means for logically combining said reset control signal and a built - in - self - test  ( BIST )  control signal into a reset - and - BIST control signal at an output thereof; and        means for controllably switching either a first input that receives a system reset signal or a second input that is connected to said output of said logically combining means to an output of said switching means under control of a normal - or - test signal that is propagated to a control input of said logically combining means; and        said output of said switching means is connected to said core logic and provides said reset signal.     
     
     
       18. An electronic device, comprising:
   an input circuit connected to a reset pin of the electronic device, comprising:        boundary - scan register means for storing a boundary - scan test information bit;        said boundary - scan register means having an inverted output of the logic level stored therein;        a logical sum means for taking a logical sum of a first inverting input that is connected to said boundary - scan register means inverted output and a second inverting input that is connected to receive a built - in - self - test  ( BIST )  control signal and providing a result at an output thereof;        a first  2   - to -   1  multiplexer having one data input connected to said output of said logical sum means, another data input connected to the reset pin, a select input connected to a normal/test pin, and an output that is multiplexed to one of said data inputs under the control of a select signal upon said select pin; and        a second logical sum means having a first inverting input connected to said first  2   - to -   1  multiplexer output and a second inverting input connected through an inverter to receive an external - test control signal, wherein said second logical sum means is for taking a logical sum of the inverse of the logic signals on its two inputs and inverting the logic sum thereof to provide a reset signal to core logic connected at an output of said second logical sum means;        whereby if said external - test control signal is at a logic low level, said reset signal to said core logic is active such that said core logic is held reset as long as said external test control signal is not at a logic low level.     
     
     
       19. A circuit apparatus providing a reset signal to core logic of an electronic device, the circuit apparatus comprising:
   storage means for storing and outputting a reset control signal;        means for logically combining the reset control signal and a built - in - self - test  ( BIST )  control signal into a reset - and - BIST control signal at an output thereof; and        means for controllably switching either a first input that receives a system reset signal or the output of the combining means or a second input that is connected to the output of the combining means to an output of the switching means under the control of a normal - or - test signal that is propagated to a control input of the logically combining means; and        wherein the output of the switching means is connected to the core logic and provides the reset signal.     
     
     
       20. The circuit apparatus of  claim 19 , wherein the storage means is a transparent latch. 
     
     
       21. The circuit apparatus of  claim 20 , wherein the combining means is an OR gate having a plurality of inverting inputs and a non- inverting output.   
     
     
       22. The circuit apparatus of  claim 21 , wherein the switching means is a  2 - to -   1  multiplexer.   
     
     
       23. The circuit apparatus of  claim 22 , wherein the transparent latch is resettable. 
     
     
       24. The circuit apparatus of  claim 23 , wherein an output of the transparent latch is an inverting output. 
     
     
       25. The circuit apparatus of  claim 19 , further comprising second means for combining the reset signal output from the output of the switching means and an external test control signal. 
     
     
       26. The circuit apparatus of  claim 25 , wherein the second logically combining means is an OR gate, and wherein the OR gate has a plurality of inverting inputs and an inverted output. 
     
     
       27. An input circuit connected to a reset pin of an electronic device, comprising:
   boundary - scan register means for storing a boundary - scan test information bit, wherein the boundary - scan register means has an inverted output of the logic level stored therein;        a first logical sum means for taking a logical sum of a first inverting input connected to the inverted output of the boundary - scan register means and a second inverting input that receives a built - in - self - test  ( BIST )  control signal and providing a result at an output thereof;        a first  2   - to -   1  multiplexer having one data input connected to the output of the first logical sum means, another data input connected to an input reset pin, a select input connected to a normal/test pin and configured to receive a normal/test signal, and an output that is multiplexed to one of the data inputs under the control of the normal/test signal;        a second logical sum means having a first inverting input connected to the first  2   - to -   1  multiplexer output and a second inverting input connected through an inverter to an external - test control signal, wherein the second logical sum means takes a logical sum of the inverses of the logic signals on its two inputs and inverts the logic sum thereof to output a reset signal to core logic connected to an output of the second logical sum means;        wherein when the external - test control signal is at a logic low level, the outputted reset signal to the core logic is active such that the core logic is held reset as long as the external test control signal is at a logic level other than the logic low level.     
     
     
       28. The input circuit of  claim 27 , further comprising a second  2 - to -   1  multiplexer, included as part of the boundary - scan register means, having one data input connected to a serial data input, another data input connected to the output of the first  2   - to -   1  multiplexer, and a select input that receives a shift select control signal, wherein the shift control signal selects either the serial data input signal or the output signal of the first  2   - to -   1  multiplexer as a logic level to be stored in the boundary - scan register means.   
     
     
       29. The input circuit of  claim 27 , wherein when the output of the first  2 - to -   1  multiplexer is at a logic low level, the outputted reset signal is active such that said core logic is held reset as long as the first  2   - to -   1  multiplexer output is at a logic low level.   
     
     
       30. The input circuit of  claim 29 , wherein the boundary- scan register means has an asynchronous reset input that causes the inverted output of the boundary - scan register means to be a logic high signal when the asynchronous input is driven to a logic low level.   
     
     
       31. The input circuit of  claim 27 , wherein the boundary- scan register means includes a type D flip - flop and a latch, and wherein a data input of the latch is connected to a non - inverted output of the type D flip - flop.   
     
     
       32. The input circuit of  claim 27 , wherein the first logical sum means is an OR gate having inverting inputs and the second logical sum means is an OR gate having inverting inputs and an inverted output.