Method and apparatus for operating a CMOS imager having a pipelined analog to digital converter

Abstract

An image sensor system using offset analog to digital converters. The analog to digital converters require a plurality of clock cycles to carry out the actual conversion. These conversions are offset in time from one another, so that at each clock cycle, new data is available. A system includes a CMOS active pixel image sensor having an array for photoreceptors to convert an image into an analog signal. The CMOS image sensor converts the analog signal into a digital signal using a pipelined analog to digital converter.

What is claimed is:  
     
       1. An analog-to-digital (A/D) converter, comprising:
 an input, for receiving a series of analog signals;  
 an output, for outputting a series of digital signals respectively corresponding to said series of analog signals;  
 a plurality of A/D cells, each of said A/D cells for converting one of said series of analog signals to a corresponding one of said series of digital signals; and  
 a control circuit, coupled to said input, said output, and said plurality of A/D cells;  
 wherein said control circuit operates said input, said output, and said plurality of A/D cells so that each successive A/D cell is assigned, at a different time, to convert a different one of each successive analog signal from said series of analog signals to a corresponding digital signal in said series of digital signals.  
 
     
     
       2. The analog-to-digital converter of  claim 1 , wherein said different time correspond to a different period of a clock signal provided to said analog-to-digital converter. 
     
     
       3. The analog-to-digital converter of  claim 1 , wherein each of said A/D cells further comprises a calibration element, said calibration element being set so that each A/D cell coverts the same analog signal present at said input to a same digital value at said output. 
     
     
       4. The analog-to-digital converter of  claim 1 , wherein each of said A/D cells further comprises a noise suppression element. 
     
     
       5. The analog-to-digital converter of  claim 4 , wherein said noise suppression element comprises a transistor. 
     
     
       6. The analog-to-digital converter of  claim 1 , wherein each A/D cell performs an A/D conversion in a same amount of time. 
     
     
       7. The analog-to-digital converter of  claim 1 , wherein each A/D cell performs an A/D conversion using successive approximation. 
     
     
       8. The analog-to-digital converter of  claim 1 , wherein said control circuit operates to cause said analog-to-digital converter to begin converting a different one of said series of analog signals on each of a series of successive clock signals. 
     
     
       9. The analog-to-digital converter of  claim 1 , wherein said control circuit operates to cause said analog-to-digital converter to output a series of digital signals on each of a series of successive clock signals. 
     
     
       10. A method for converting a series of analog signals to a corresponding series of digital signals, comprising:
 receiving over a period of time, a series of analog signals;    assigning each analog signal from said series of analog signals as they are received to an available A/D cell for analog-to-digital conversion to a corresponding digital signal; and    outputting a different digital signal corresponding to a respective analog signal from said series of analog signals as each A/D cell finishes its analog-to-digital conversion;    wherein at least two A/D cells are performing respective analog-to-digital conversions while another A/D cell outputs one of said digital signals.    
     
     
       11. The method of  claim 10 , further comprising:
 calibrating each A/D cell so that an analog-to-digital conversion performed on a same analog signal by any A/D cell results in a same digital signal.    
     
     
       12. The method of  claim 10 , wherein said step of assigning comprises a step of suppressing comparator kickback noise during said analog-to-digital conversion. 
     
     
       13. The method of  claim 10 , wherein each A/D cell performs an analog-to-digital conversion in a same amount of time. 
     
     
       14. The method of  claim 10 , wherein each A/D cell perform an analog-to-digital conversion using successive approximation. 
     
     
       15. An apparatus comprising:
   a CMOS active pixel array to convert an image into a plurality of successive analog signals;        an analog to digital  ( A/D )  converter comprising a plurality of A/D converter cells; and        a controller to assign each one of the plurality of successive analog signals to a respective one of the plurality of A/D converter cells such that each one of the plurality of A/D converter cells is configured to convert the respective one of the plurality of successive analog signals to a respective one of a plurality of successive digital signals during time periods that are offset and partially overlapping.      
     
     
       16. The apparatus of  claim 15 , wherein each of the plurality of successive analog signals represents a respective pixel of the image.  
     
     
       17. The apparatus of  claim 15 , wherein the A/D converter is disposed on the same chip as the CMOS active pixel array.  
     
     
       18. The apparatus of  claim 17 , wherein each of the plurality of A/D converter cells is a successive approximation A/D converter cell.  
     
     
       19. The apparatus of  claim 15 , wherein each of the plurality of A/D converter cells is a successive approximation A/D converter cell.  
     
     
       20. The apparatus of  claim 19 , wherein each of the time periods are offset by one clock cycle.  
     
     
       21. The apparatus of  claim 15 , wherein each of the time periods are offset by one clock cycle.  
     
     
       22. The apparatus of  claim 15 , wherein the active pixel array comprises an array of photodiodes.  
     
     
       23. An apparatus comprising:
   an array of photodiodes of a CMOS active pixel sensor to convert light forming at least a portion of an image into first, second, and third analog signals; and        an analog to digital  ( A/D )  converter operating in a pipelined fashion, the A/D converter comprising:      an input to receive the first, second, and third analog signals at first, second, and third times, respectively, wherein the first, second, and third times are offset in time from one another; and        an output to provide at least a respective first bit of respective first, second, and third digital signals corresponding to the first, second, and third analog signals, respectively, at fourth, fifth, and sixth times, respectively, wherein the fourth, fifth, and sixth times are offset in time from one another and occur after the first, second, and third times.        
     
     
       24. The apparatus of  claim 23 , wherein the first, second, and third analog signals represent first, second, and third pixels, respectively, of the image.  
     
     
       25. The apparatus of  claim 24 , wherein the A/D converter comprises a plurality of successive approximation A/D converter cells.  
     
     
       26. The apparatus of  claim 25 , wherein the A/D converter is disposed on the same chip as the array of photodiodes.  
     
     
       27. The apparatus of  claim 26 , wherein each the first, second, and third times are offset by one clock cycle.  
     
     
       28. The apparatus of  claim 23 , wherein each the first, second, and third times are offset by one clock cycle.