USRE41538EExpiredUtilityPatentIndex 62

Method for making integrated circuit including interconnects with enhanced electromigration resistance using doped seed layer and integrated circuits produced thereby

Assignee: CUNNINGHAM JAMES APriority: Jul 22, 1999Filed: Apr 22, 2005Granted: Aug 17, 2010

Est. expiryJul 22, 2019(expired)· nominal 20-yr term from priority

Inventors:CUNNINGHAM JAMES A

H10W 20/0425H10W 20/0526H10W 20/425H10W 20/064H10W 20/056H10W 20/049H10W 20/043H10W 20/42H10W 20/037H10W 20/033

PatentIndex Score

Cited by

References

Claims

Abstract

A method for making an integrated circuit device includes forming at least one interconnect structure adjacent a substrate by forming at least one barrier layer, forming a doped copper seed layer on the at least one barrier layer, and forming a copper layer on the doped copper seed layer. The method may further include annealing the integrated circuit device after forming the copper layer to diffuse the dopant from the doped copper seed layer into grain boundaries of the copper layer. The doped copper seed layer may include at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant to provide the enhanced electromigration resistance. Forming the copper layer may comprise plating the copper layer. In addition, forming the copper layer may comprise forming the copper layer to include at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant. In some embodiments, the dopant in the seed layer may be sufficient so that no additional dopant is needed in the copper layer.

Claims

exact text as granted — not AI-modified

1. A method for making an integrated circuit device, comprising:
forming at least one interconnect structure adjacent a substrate by , wherein said forming at least one interconnect structure comprises:
forming at least one barrier layer, ;
forming a doped copper seed layer on the at least one barrier layer, wherein the doped copper seed layer including includes a dopant comprising at least one of calcium, cadmium, neodymium, or tellurium, and ytterbium, ; and
forming a copper layer on the doped copper seed layer.

2. A method according to claim 1 further comprising annealing the integrated circuit device after forming the copper layer to diffuse the dopant from the doped copper seed layer into grain boundaries of the copper layer.

3. A method according to claim 1 wherein forming the copper layer comprises plating the copper layer.

4. A method according to claim 1 wherein forming the copper layer comprises forming the copper layer to include a dopant comprising at least one of calcium, cadmium, zinc, neodymium, tellurium, and or ytterbium.

5. A method according to claim 1 , further comprising:
forming at least one dielectric layer adjacent the a substrate; and
forming at least one opening in the at least one dielectric layer for receiving the at least one interconnect structure therein.

6. A method according to claim 1 wherein forming the at least one barrier layer comprises forming at least one barrier layer comprising metal.

7. A method according to claim 1 wherein forming the at least one barrier layer comprises forming at least one barrier layer comprising at least one of tantalum nitride and or tantalum silicon nitride.

8. A method according to claim 1 wherein forming the at least one barrier layer comprises forming at least one barrier layer comprising cobalt and phosphorous.

9. A method according to claim 1 further comprising forming a displacement plated copper layer on which the at least one barrier layer is formed.

10. A method for making an integrated circuit device, comprising:
forming at least one interconnect structure adjacent a substrate by , wherein said forming at least one interconnect structure comprises:
forming at least one metal barrier layer, ;
forming a doped copper seed layer on the at least one metal barrier layer, wherein the doped copper seed layer including includes a dopant comprising at least one of calcium, cadmium, neodymium, or tellurium, and ytterbium, ; and
forming a copper layer on the doped copper seed layer.

11. A method according to claim 10 further comprising annealing the integrated circuit device after forming the copper layer to diffuse the dopant from the doped copper seed layer into grain boundaries of the copper layer.

12. A method according to claim 10 wherein forming the copper layer comprises plating the copper layer.

13. A method according to claim 10 wherein forming the copper layer comprises forming the copper layer to include a dopant comprising at least one of calcium, cadmium, zinc, neodymium, tellurium, and or ytterbium.

14. A method according to claim 10 , further comprising:
forming at least one dielectric layer adjacent the a substrate; and
forming at least one opening in the at least one dielectric layer for receiving the at least one interconnect structure therein.

15. A method according to claim 10 wherein forming the at least one metal barrier layer comprises forming at least one metal barrier layer comprising at least one of tantalum nitride and or tantalum silicon nitride.

16. A method according to claim 10 wherein forming the at least one metal barrier layer comprises forming at least one metal barrier layer comprising cobalt and phosphorous.

17. A method according to claim 10 further comprising forming a displacement plated copper layer on which the at least one metal barrier layer is formed.

18. A method for making an integrated circuit device, comprising:
forming at least one interconnect structure adjacent a substrate by , wherein said forming at least one interconnect structure comprises:
forming at least one barrier layer, ;
forming a doped copper seed layer on the at least one barrier layer, wherein the doped copper seed layer including includes a dopant comprising at least one of calcium, cadmium, neodymium, tellurium, and or ytterbium, ;
plating a copper layer on the doped copper seed layer, wherein the doped copper seed layer has a higher dopant concentration than the copper layer; and
annealing the integrated circuit device after forming the copper layer to diffuse the dopant from the doped copper seed layer into the copper layer.

19. A method according to claim 18 , further comprising doping the copper layer with at least one of calcium, cadmium, zinc, neodymium tellurium, and or ytterbium prior to annealing.

20. A method according to claim 18 , further comprising:
forming at least one dielectric layer adjacent the a substrate; and
forming at least one opening in the at least one dielectric layer for receiving the at least one interconnect structure therein.

21. A method according to claim 18 wherein forming the at least one barrier layer comprises forming at least one barrier layer comprising metal.

22. A method according to claim 18 wherein forming the at least one barrier layer comprises forming at least one barrier layer comprising at least one of tantalum nitride and or tantalum silicon nitride.

23. A method according to claim 18 wherein forming the at least one barrier layer comprises forming at least one barrier layer comprising cobalt and phosphorous.

24. A method according to claim 18 further comprising forming a displacement plated copper layer on which the at least one barrier layer is formed.

25. A method for making an integrated circuit device, comprising:
forming at least one interconnect structure, wherein said forming at least one interconnect structure comprises: forming a plating layer on a first copper - containing layer, wherein the plating layer includes a metal more noble than copper; forming at least one barrier layer on the plating layer; forming a doped copper seed layer including at least one dopant comprising calcium, cadmium, zinc, neodymium, tellurium, or ytterbium; and forming a second copper - containing layer on the doped copper seed layer.

26. The method of claim 25 , further comprising annealing the integrated circuit device after forming the second copper- containing layer to diffuse the dopant from the doped copper seed layer at least into grain boundaries of the copper - containing layer.

27. The method of claim 25 wherein said forming a second copper- containing layer comprises plating the second copper - containing layer.

28. The method of claim 25 wherein said forming a second copper- containing layer comprises forming the second copper - containing layer to include at least one dopant comprising calcium, cadmium, zinc, neodymium, tellurium, or ytterbium.

29. The method of claim 25 wherein said forming a second copper- containing layer comprises forming the second copper - containing layer without any calcium, cadmium, zinc, neodymium, tellurium, or ytterbium dopant therein.

30. The method of claim 25 , further comprising:
forming at least one dielectric layer; and forming at least one opening in the at least one dielectric layer for receiving at least part of the at least one interconnect structure therein.

31. The method of claim 25 wherein said forming at least one barrier layer comprises forming the at least one barrier layer comprising metal.

32. The method of claim 25 wherein said forming at least one barrier layer comprises forming the at least one barrier layer comprising at least one of tantalum nitride or tantalum silicon nitride.

33. The method of claim 25 wherein said forming at least one barrier layer comprises forming the at least one barrier layer comprising at least cobalt and phosphorous.

34. The method of claim 25 , further comprising annealing the plating layer to drive the more noble metal into the first copper- containing layer.

35. The method of claim 25 wherein said forming at least one interconnect structure comprises forming the at least one interconnect structure adjacent to a substrate.

36. The method of claim 25 wherein the doped copper seed layer is formed on the at least one barrier layer.

37. The method of claim 25 wherein said forming a doped copper seed layer comprises forming the doped copper seed layer to include a dopant comprising calcium and at least one of cadmium, neodymium, tellurium, or ytterbium.

38. The method of claim 25 wherein said forming a doped copper seed layer comprises forming the doped copper seed layer to include a dopant comprising cadmium and at least one of calcium, neodymium, tellurium, or ytterbium.

39. The method of claim 25 wherein said forming a doped copper seed layer comprises forming the doped copper seed layer to include a dopant comprising neodymium and at least one of calcium, cadmium, tellurium, or ytterbium.

40. The method of claim 25 wherein said forming a doped copper seed layer comprises forming the doped copper seed layer to include a dopant comprising tellurium and at least one of calcium, cadmium, neodymium, or ytterbium.

41. The method of claim 25 wherein said forming a doped copper seed layer comprises forming the doped copper seed layer to include a dopant comprising ytterbium and at least one of calcium, cadmium, neodymium, or tellurium.

42. The method of claim 25 wherein said forming at least one barrier layer comprises forming the at least one barrier layer to include tantalum.

43. A method for making an integrated circuit device, comprising:
forming at least one interconnect structure, wherein said forming at least one interconnect structure comprises: forming at least one barrier layer; forming a doped copper seed layer including at least one dopant comprising calcium, cadmium, zinc, neodymium, tellurium, or ytterbium; and forming a copper - containing layer over the doped copper seed layer, wherein at least a portion of the copper - containing layer is plated with a plating layer including a metal more noble than copper.

44. The method of claim 43 , further comprising annealing the integrated circuit device after forming the copper- containing layer to diffuse the dopant from the doped copper seed layer at least into grain boundaries of the copper - containing layer.

45. The method of claim 43 , further comprising annealing the plating layer to drive the more noble metal into the copper- containing layer.

46. The method of claim 43 wherein said forming a copper- containing layer comprises forming the copper - containing layer to include at least one dopant comprising calcium, cadmium, zinc, neodymium, tellurium, or ytterbium.

47. The method of claim 43 , wherein said forming a copper- containing layer comprises forming the copper - containing layer without any calcium, cadmium, zinc, neodymium, tellurium, or ytterbium dopant therein.

48. The method of claim 43 , further comprising:
forming at least one dielectric layer; and forming at least one opening in the at least one dielectric layer for receiving the at least one interconnect structure therein.

49. The method of claim 43 , wherein said forming at least one barrier layer comprises forming the at least one barrier layer comprising at least one of tantalum nitride or tantalum silicon nitride.

50. The method of claim 43 , wherein forming at least one barrier layer comprises forming the at least one barrier layer comprising at least cobalt and phosphorous.

51. The method of claim 43 , further comprising forming a displacement plated copper- containing layer on which the at least one barrier layer is formed.

52. The method of claim 43 , wherein said forming at least one interconnect structure comprises forming the at least one interconnect structure adjacent to a substrate.

53. The method of claim 43 , wherein the doped copper seed layer is formed on the at least one barrier layer.

54. A method for making an integrated circuit device, comprising:
forming at least one interconnect structure, wherein said forming at least one interconnect structure comprises: forming at least one barrier layer; forming a doped copper seed layer including at least one dopant configured to provide enhanced electromigration resistance; forming a copper - containing layer on the doped copper seed layer, wherein the doped copper seed layer has a higher dopant concentration than the copper - containing layer; and annealing the integrated circuit device after forming the copper - containing layer to diffuse the dopant from the doped copper seed layer at least into the copper - containing layer.

55. The method of claim 54 , further comprising doping the copper- containing layer with at least one of calcium, cadmium, zinc, neodymium tellurium, or ytterbium prior to annealing.

56. The method of claim 54 , wherein said forming a copper- containing layer comprises forming the copper - containing layer without any calcium, cadmium, zinc, neodymium, tellurium, or ytterbium dopant therein.

57. The method of claim 54 , further comprising:
forming at least one dielectric layer; and forming at least one opening in the at least one dielectric layer for receiving the at least one interconnect structure therein.

58. The method of claim 54 , wherein said forming at least one barrier layer comprises forming the at least one barrier layer comprising metal.

59. The method of claim 54 , wherein said forming at least one barrier layer comprises forming the at least one barrier layer comprising at least one of tantalum nitride or tantalum silicon nitride.

60. The method of claim 54 , wherein said forming at least one barrier layer comprises forming the at least one barrier layer comprising at least cobalt and phosphorous.

61. The method of claim 54 , further comprising forming a displacement plated copper- containing layer on which the at least one barrier layer is formed.

62. The method of claim 54 , wherein said forming at least one interconnect structure comprises forming the at least one interconnect structure adjacent to a substrate.

63. The method of claim 54 , wherein the doped copper seed layer is formed on the at least one barrier layer.

64. A method for making an integrated circuit device, comprising:
forming at least one interconnect structure, wherein said forming at least one interconnect structure comprises: forming at least one barrier layer; forming a doped copper seed layer including at least one dopant configured to provide enhanced electromigration resistance; and forming a copper - containing layer over the doped copper seed layer, wherein at least a portion of the copper - containing layer is plated with a plating layer including a metal more noble than copper.

65. The method of claim 64 , further comprising annealing the integrated circuit device after forming the copper- containing layer to diffuse the dopant from the doped copper seed layer at least into grain boundaries of the copper - containing layer.

66. The method of claim 64 , wherein the dopant comprises at least one of calcium, cadmium, neodymium, tellurium, or ytterbium.

67. The method of claim 64 , further comprising annealing the plating layer to drive the more noble metal into the copper- containing layer.

68. The method of claim 64 , wherein said forming a copper- containing layer comprises forming the copper - containing layer to include a dopant comprising at least one of calcium, cadmium, zinc, neodymium, tellurium, or ytterbium.

69. The method of claim 64 , further comprising:
forming at least one dielectric layer; and forming at least one opening in the at least one dielectric layer for receiving the at least one interconnect structure therein.

70. The method of claim 64 , wherein said forming at least one barrier layer comprises forming the at least one barrier layer comprising metal.

71. The method of claim 64 , wherein said forming at least one barrier layer comprises forming the at least one barrier layer comprising at least one of tantalum nitride or tantalum silicon nitride.

72. The method of claim 64 , wherein said forming at least one barrier layer comprises forming the at least one barrier layer comprising at least cobalt and phosphorous.

73. The method of claim 64 , further comprising forming a displacement plated copper layer on which the at least one barrier layer is formed.

74. The method of claim 64 , wherein said forming at least one interconnect structure comprises forming the at least one interconnect structure adjacent to a substrate.

75. The method of claim 64 , wherein the doped copper seed layer is formed on the at least one barrier layer.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.