Single chip frame buffer and graphics accelerator

Abstract

A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.

1. A single chip display processor comprising:
 (a) a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data,    (b) a pixel data unit (PDU) for processing said pixel data, integrated in the same integrated circuit (IC) chip as the DRAM,    (c) said IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU,    
       whereby the PDU can process said blocks of pixel data for subsequent display of processed pixel data,
 (d) said DRAM comprising rows of wordlines, columns of bitlines which are orthogonal to said rows of bitlines, bit storage cells connected to said bitlines and wordlines each for storage of a bit of said pixel data, and rows of sense amplifiers connected to the bitlines, sense amplifier select lines connected to groups of said sense amplifiers for enabling operation of said groups of said sense amplifiers together, said sense amplifier and select lines being carried by said IC chip parallel to said wordlines, data bus lines constituting said massively parallel bus each being respectively connected to an output of a sense amplifier and being carried by said IC chip parallel to said bitlines,  
 (e) the PDU being pitch matched to four bitline columns, and being comprised of single bit PDU processors, each virtually simultaneously receiving a bit from a corresponding databus for parallel processing thereof.  
 
     
     
       2. A single chip display processor comprising:
 (a) a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data,    (b) a pixel data unit (PDU) for processing said pixel data, integrated in the same integrated circuit (IC) chip as the DRAM,    (c) said IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU,    
       whereby the PDU can process said blocks of pixel data for subsequent display of processed pixel data,
 (d) said DRAM comprising rows of wordlines, columns of bitlines which are orthogonal to said rows of bitlines, bit storage cells connected to said bitlines and wordlines each for storage of a bit of said pixel data, and rows of sense amplifiers connected to the bitlines, sense amplifier select lines connected to groups of said sense amplifiers for enabling operation of said groups of said sense amplifiers together, said sense amplifier and select lines being carried by said IC chip parallel to said wordlines, data bus lines constituting said massively parallel bus each being respectively connected to an output of a sense amplifier and being carried by said IC chip parallel to said bitlines, the PDUs being pitch matched to a predetermined number of bitlines columns,  
 (e) each PDU being comprised of plural PDU units, each unit being comprised of a single bit PDU processor, each PDU processor being connected to a databus for receiving a logical bit from a sense amplifier, and  
 (f) a PDU address decoder for enabling operation at the same time of any number of PDU processors having adjacent addresses, whereby any width of data from any adjacent bitlines may be written into said any number of PDU processors or any width of said number of PDU processors may be cleared in a single cycle.  
 
     
     
       3. A single chip display processor comprising:
 (a) a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data,    (b) a pixel data unit (PDU) for processing said pixel data, integrated in the same integrated circuit (IC) chip as the DRAM,    (c) said IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU,    
       whereby the PDU can process said blocks of pixel data for subsequent display of processed pixel data,
 (d) said DRAM comprising rows of wordlines, columns of bitlines which are orthogonal to said rows of bitlines, bit storage cells connected to said bitlines and wordlines each for storage of a bit of said pixel data, and rows of sense amplifiers connected to the bitlines, sense amplifier select lines connected to groups of said sense amplifiers for enabling operation of said groups of said sense amplifiers together, said sense amplifier and select lines being carried by said IC chip parallel to said wordlines, data bus lines constituting said massively parallel bus each being respectively connected to an output of a sense amplifier and being carried by said IC chip parallel to said bitlines, the PDUs being pitch matched to a predetermined number of bitlines columns,  
 (e) each PDU being comprised of plural PDU units, each unit being comprised of a single bit PDU processor, each PDU processor being connected to a databus for receiving a logical bit from a sense amplifier, and  
 (f) each PDU unit being further comprised of one-bit source, destination and brush variable registers, a four input raster operation (ROP4) circuit for logically operating on bits stored in said registers, an ROP4 register for storing output data of the ROP4 circuit, and a mask register for masking output data of the PDU processors, each register being connected to the ROP4 circuit, the ROP4 circuit and each register being pitch matched to four bitline columns and connected to a databus.  
 
     
     
       4. A processor as defined in  claim 3  in which each of the source, destination and brush variable registers is comprised of a cross-coupled inverter connected to each data bus through a memory access circuit via a pair of NMOS transistors. 
     
     
       5. A processor as defined in  claim 3  in which each of the source, destination and brush variable registers is two ported, and is comprised of a cross-coupled inverter connected from one port to a corresponding data bus through a memory circuit via a pair of NMOS transistors, and being connected from a second port to a register bus connected to the ROP4 circuit. 
     
     
       6. A processor as defined in  claim 5  in which each inverter is comprised of VDD voltage power and VSS ground inputs, and further including, to implement a write cycle to an inverter, means for equalizing said power and ground inputs at a voltage of ½ VDD, applying input data to one of said registers bus, selecting the register, then raising the power and ground inputs to VDD and VSS respectively. 
     
     
       7. A processor as defined in  claim 6  including, to implement a read cycle, precharging the register bus to VDD prior to reading the register. 
     
     
       8. A processor as defined in  claim 6  including, to implement a read cycle, applying in place of a power voltage of VDD, a VPP voltage which is greater than: an NMOS transistor operation threshold voltage which is (V t ) higher than VDD. 
     
     
       9. A single chip display processor comprising:
 (a) a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data,    (b) a pixel data unit (PDU) for processing said pixel data, integrated in the same integrated circuit (IC) chip as the DRAM,    (c) said IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU,    
       whereby the PDU can process said blocks of pixel data for subsequent display of processed pixel data,
 (d) each of the PDUs comprising at least one register, each of the registers being comprised of a cross-coupled inverter connected via access means to a pair of databus lines, each inverter being comprised of VDD and VSS ground inputs, means for implementing a cycle accessing each inverter to the pair of data buslines by precharging the databus lines to a voltage intermediate the difference between VDD and VSS, selecting each register to connect its inverter to the pair of data bus lines, and then raising the power and ground inputs to VDD and VSS respectively.  
 
     
     
       10. A processor as defined in  claim 9  in which said intermediate voltage is about VDD/2. 
     
     
       11. A single chip display processor comprising:
 (a) a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data,    (b) a pixel data unit (PDU) for processing said pixel data, integrated in the same integrated circuit (IC) chip as the DRAM,    (c) said IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU,    
       whereby the PDU can process said blocks of pixel data for subsequent display of processed pixel data,
 (d) said DRAM comprising rows of wordlines, columns of bitlines which are orthogonal to said rows of bitlines, bit storage cells connected to said bitlines and wordlines each for storage of a bit of said pixel data, and rows of sense amplifiers connected to the bitlines, sense amplifier select lines connected to groups of said sense amplifiers for enabling operation of said groups of said sense amplifiers together, said sense amplifier and select lines being carried by said IC chip parallel to said wordlines, data bus lines constituting said massively parallel bus each being respectively connected to an output of a sense amplifier and being carried by said IC chip parallel to said bitlines, the PDUs being pitch matched to a predetermined number of bitlines columns,  
 (e) means for temporarily storing data from the PDUs in the sense amplifiers connected to the bitlines during intervals when the DRAM is not in use, and  
 (f) means for transferring said data from the PDU to said sense amplifiers for temporary storage via the massively parallel bus.  
 
     
     
       12. A processor as defined in  claim 11 , in which the DRAM memory is organized into separate buffer blocks, each block storing one bit of each pixel of an entire frame of multi-bit pixels. 
     
     
       13. A processor as defined in  claim 12 , including a system bus for carrying pixel bits from a system graphics processor for writing to each of the buffer blocks individually, and for carrying pixel bits from a system graphics processor for writing the same bit values in all of the buffer blocks in a broadcast mode. 
     
     
       14. A processor as defined in  claim 12  including means for reading the buffer blocks in a fast page mode to provide output pixel data. 
     
     
       15. A processor as defined in  claim 12  in which the buffer blocks are each at least 2560 columns wide by 544 rows deep in bit capacity. 
     
     
       16. A processor as defined in  claim 12  in which the buffer blocks contain extra rows of memory for storage of at least one of scratchpad data, pixel color data, pattern data, text font data and video data. 
     
     
       17. A processor as defined in  claim 12  in which the buffer blocks are each at least 2560 columns wide by 564 rows deep in bit capacity. 
     
     
       18. A processor as defined in  claim 12 , each buffer block comprising a DRAM and an associated PDU connected to the DRAM via said massively parallel bus, the PDU being pitch matched to the DRAM. 
     
     
       19. A processor as defined in  claim 12 , including a graphics out shift register, said shift register being pitch matched to the DRAM and being connected to the DRAM via the massively parallel bus, means for transferring data in parallel from the DRAM via said bus to the graphics out shift register and for outputting said transferred data serially for processing by display circuitry. 
     
     
       20. A processor as defined in  claim 19  in which the shift register is comprised of a pair of shift register segments, means for transferring data corresponding to sequential groups of pixels to each of the pairs of shift register segments reciprocally in tandem whereby pixel data relating to a complete display line can be serially read out of the pairs of shift registers in sequential order. 
     
     
       21. A processor as defined in  claim 20  including means for reading said data out of the shift register in parallel groups of bits, and means for operating the shift register in cycles at a rate which is a fraction of a pixel data rate. 
     
     
       22. A processor as defined in  claim 20  further including a video out shift register connected to the massively parallel bus for receiving pixel data from the DRAM in parallel and for outputting the received pixel data serially for processing by display circuitry, and a video input shift register connected to the massively parallel bus for receiving serial video pixel data and for transferring it via the massively parallel bus to the DRAM. 
     
     
       23. A display processor as defined in  claim 11 , further comprising:
 (g) a processor for processing at least one of said graphics and video input pixel data,    (h) a random access memory digital to analog converter (RAMDAC) for receiving data processed by said processor and for converting it to a display signal, and    (i) said DRAM, processor and RAMDAC being integrated into the same integrated circuit chip.    
     
     
       24. A processor as defined in  claim 23  including a pixel data unit (PDU) for processing blocks of said pixel data, said PDU being integrated into said same integrated circuit chip. 
     
     
       25. A display processor as defined in  claim 11 , further comprising:
 (g) said DRAM forming a frame buffer for storing pixel data in rows,    (h) an output logic circuit for processing said pixel data,    (i) said massively parallel bus having as many bus lines as pixel bits in a row interconnecting the frame buffer and output logic circuit,    (j) a random access memory digital to analog converter (RAMDAC) connected to the output logic circuit for connecting data processed by the output logic circuit to a display signal,    (k) said frame buffer, output logic circuit, bus and RAMDAC being integrated into the same integrated circuit chip.    
     
     
       26. A single chip display processor comprising:
 (a) a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data,    (b) a pixel data unit (PDU) for processing said pixel data, integrated in the same integrated circuit (IC) chip as the DRAM,    (c) said IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU,    
       whereby the PDU can process said blocks of pixel data for subsequent display of processed pixel data,
 (d) said DRAM comprising rows of wordlines, columns of bitlines which are orthogonal to said rows of bitlines, bit storage cells connected to said bitlines and wordlines each for storage of a bit of said pixel data, and rows of sense amplifiers connected to the bitlines, sense amplifier select lines connected to groups of said sense amplifiers for enabling operation of said groups of said sense amplifiers together, said sense amplifier and select lines being carried by said IC chip parallel to said wordlines, data bus lines constituting said massively parallel bus each being respectively connected to an output of a sense amplifier and being carried by said IC chip parallel to said bitlines, the PDUs being pitch matched to a predetermined number of bitlines columns,  
 (e) each bitline column of the DRAM comprising plural transmitting and receiving sense amplifiers respectively, each connected to a bitline pair, said plural sense amplifiers being connected in parallel to an operational pair of data bus lines of an operational data bus, and further comprising a dummy data bus comprised of a dummy pair of data bus lines, means for enabling the plural transmitting sense amplifiers to dump data to the operational pair of data bus lines and for equalizing the voltage on a corresponding bitline pair to VDD/2 voltage, means for charging the dummy pair of data bus lines in parallel with the operational pair of data bus lines, means for detecting when the charge on the dummy pair of databus lines is readable and for providing a signal for disabling the transmitting sense amplifiers and enabling the receiving sense amplifiers, whereby the voltage on the operational pair of data bus lines is inhibited from rising to a level higher than is necessary for correct reading of its data.  
 
     
     
       27. A single chip display processor comprising:
 ( a )  a dynamic random access memory  ( DRAM )  frame buffer for storing at least one of graphics and video pixel data;      ( b )  a graphics processor for processing in hardware the pixel data according to instructions required by a graphical user interface or operating system, integrated in the same integrated circuit  ( IC )  chip as the DRAM; and      ( c )  the IC chip further comprising a limited - voltage swing parallel bus electrically connected to a plurality of sense amplifiers within the DRAM, the limited voltage swing parallel bus comprising a real databus and a dummy databus for determining when a voltage on the real databus is split sufficiently for reading by a receiving sense amplifier, and for transferring, in parallel blocks, pixel data from the DRAM frame buffer to the graphics processor and from the graphics processor to the DRAM,        whereby the graphics processor can process the blocks of pixel data for subsequent display of processed pixel data, and for writing the processed pixel data into the frame buffer.     
     
     
       28. The single chip display processor as claimed in  claim 27 , wherein transmitting and receiving sense amplifiers are coupled to the limited voltage swing parallel bus. 
     
     
       29. The single chip display processor as claimed in  claim 28 , wherein the transmitting and receiving sense amplifiers each comprise cross- coupled inverters.   
     
     
       30. The single chip display processor as claimed in  claim 27 , wherein a voltage swing of the real databus is substantially less than V DD   −V   SS . 
     
     
       31. The single chip display processor as claimed in  claim 27 , wherein a voltage swing of the dummy databus is substantially less than V DD   −V   SS . 
     
     
       32. The single chip display processor as claimed in  claim 27 , wherein a differential amplifier is connected to the dummy databus. 
     
     
       33. The single chip display processor as claimed in  claim 32 , wherein a size of the differential amplifier is chosen to detect when the dummy databus is readable. 
     
     
       34. The single chip display processor as claimed in  claim 32 , wherein an offset of the differential amplifier is chosen to be in a range of  200  mV to  500  mV. 
     
     
       35. The single chip display processor as claimed in  claim 27 , wherein a plurality of access transistors connected to the dummy databus are substantially the same size respectively as a plurality of access transistors connected respectively to the real databus. 
     
     
       36. The single chip display processor as claimed in  claim 35 , wherein a plurality of pull- down transistors connected respectively to the plurality access transistors connected to the dummy databus are substantially the same size respectively as a plurality of pull - down transistors connected respectively to the plurality of access transistors connected to the real databus.   
     
     
       37. A single chip display processor comprising:
 ( a )  a dynamic random access memory  ( DRAM )  frame buffer for storing at least one of graphics and video pixel data;      ( b )  a graphics processor for processing in hardware the pixel data according to instructions required by a graphical user interface or operating system, integrated in the same integrated circuit  ( IC )  chip as the DRAM; and      ( c )  the IC chip further comprising a limited - voltage swing parallel bus electrically connected to a plurality of sense amplifiers within the DRAM, for transferring, in parallel blocks, pixel data from the DRAM frame buffer to the graphics processor and from the graphics processor to the DRAM, a voltage swing of the limited voltage swing parallel bus being self timed;        whereby the graphics processor can process the blocks of pixel data for subsequent display of processed pixel data, and for writing the processed pixel data into the frame buffer.     
     
     
       38. A method for executing a register transfer over a limited voltage swing parallel bus in a single chip display processor, the method comprising the steps of:
   pre - charging a real databus to a predetermined voltage;        pre - charging a dummy databus to a predetermined voltage;        pre - charging a plurality of register bits to a predetermined voltage;        disabling the pre - charging of the real databus, the dummy databus and the plurality of register bits;        enabling a transmitting sense amplifier for dumping charge into the real databus;        equalizing a receiving sense amplifier coupled to the real databus;        sensing a readable signal on the dummy databus; and        disabling the transmitting sense amplifier and enabling the receive sense amplifier.     
     
     
       39. The method for executing a register transfer over a limited voltage swing parallel bus in a single chip display processor as claimed in  claim 38  comprising the step of pre- charging the real data bus to about V   DD   / 2 .   
     
     
       40. The method for executing a register transfer over a limited voltage swing parallel bus in a single chip display processor as claimed in  claim 38  comprising the step of pre- charging the dummy databus to about V   DD   / 2 .   
     
     
       41. The method for executing a register transfer over a limited voltage swing parallel bus in a single chip display processor as claimed in  claim 38  comprising the step of pre- charging the plurality of registers bits to about V   DD   / 2 .   
     
     
       42. The method for executing a register transfer over a limited voltage swing parallel bus in a single chip display processor as claimed in  claim 38 , wherein the steps of enabling the transmitting sense amplifier and equalizing the receiving sense amplifier are executed in parallel.