Monolithic low dielectric constant platform for passive components and method

Abstract

A method for forming a low dielectric constant insulator in a monolithic substrate and the dielectric formed by the method. The method includes formation and patterning of a mask on a silicon substrate followed by anisotropic etching of the silicon to provide a dense array of deep holes. Isotropic etching may be used to form a cavity beneath the dense array of holes and coupling to bottoms of the holes. Sides of the holes are then thermally oxidized. A conventional dielectric is then formed, sealing tops of the holes. The conventional dielectric is optionally densified. Conventional chemical-mechanical polishing then planarizes the dielectric and further conventional processing may be carried out on the wafer to form active circuitry together with passive components such as high Q inductors.

1. A method for forming a dielectric platform in a silicon substrate comprising:
 forming a mask on a top surface of the substrate;    etching an array of holes in the substrate using the mask, the holes each having a depth greater than a width of the holes, the width of the holes being less than two microns;    oxidizing sidewalls of the holes to provide a dielectric lattice, sidewalls of the holes being formed from silicon dioxide and having a thickness of less than one micron;    forming a subsurface cavity in the substrate beneath the dielectric lattice;    forming a seal at taps of the holes, sealing the holes and the subsurface cavity; and    planarizing a top surface of the seal using a chemical-mechanical polish.    
     
     
       2. The method of  claim 1  wherein planarizing includes planarizing the top surface of the seal to be coplanar with a top surface of the silicon substrate. 
     
     
       3. A method for forming a subsurface cavity in a semiconductor substrate, comprising:
 defining a surface region corresponding to the subsurface cavity;  
 forming a plurality of openings in the surface region to a first depth with a first etch step;  
 forming a dielectric layer in the plurality of openings; 
 providing etchant in a second etch step through the plurality of openings to form the subsurface cavity beneath the surface region; and  
 forming a dielectric layer on the surface region to seal the subsurface cavity.  
 
     
     
       4. The method of  claim 3 , wherein forming a dielectric layer comprises forming an oxide layer. 
     
     
       5. The method of  claim 3 , wherein forming a dielectric layer comprises oxidizing at least portions of the semiconductor substrate. 
     
     
       6. A method for forming a device support structure in a semiconductor substrate comprising:
 forming a pattern of openings in a region of the semiconductor substrate wherein an opening in the interior of the region is spaced substantially equidistant in all directions from adjacent openings;  
 forming an oxide layer in the pattern of openings to form an oxide lattice which corresponds to the device support structure; and  
 capping the oxide lattice to seal the pattern of openings.  
 
     
     
       7. The method of  claim 6  further including planarizing a surface of the oxide lattice such that an upper surface of the oxide lattice is planar to a surface of the semiconductor substrate. 
     
     
       8. The method of  claim 6  further including providing etchant through the pattern of openings to form a subsurface cavity in the semiconductor substrate. 
     
     
       9. The method of  claim 6  including forming a device overlying the oxide lattice. 
     
     
       10. The method of  claim 3 , further comprising oxidizing sidewalls of the plurality of openings and wherein forming a dielectric layer comprises forming an oxide layer using a TEOS process. 
     
     
       11. A method, comprising:
   forming a dielectric platform in a silicon substrate, wherein the forming of the dielectric platform comprises:      etching a silicon substrate to form a plurality of sidewalls having portions of the silicon substrate between the plurality of sidewalls, wherein the plurality of sidewalls extend from a surface of the silicon substrate into the silicon substrate a distance of at least about three microns; and        oxidizing the portions of the silicon substrate between the sidewalls to convert substantially all of the portions of the silicon substrate between the sidewalls to silicon dioxide; and          forming an active electrical component in an area of the silicon substrate adjacent to dielectric platform after the forming of the dielectric platform.     
     
     
       12. The method of  claim 11 , wherein oxidizing the sidewalls includes oxidizing the sidewalls so that the dielectric constant of the dielectric platform is less than the dielectric constant of silicon dioxide. 
     
     
       13. The method of  claim 11 , wherein a thickness of the silicon substrate between the plurality of sidewalls is between  0 . 1  to  0 . 4  [less than about one] micron. 
     
     
       14. The method of  claim 11 , wherein forming the active electrical component includes forming a transistor and further comprising forming a passive electrical component over the dielectric platform. 
     
     
       15. The method of  claim 14 , wherein forming a passive electrical component comprises forming an inductor, a capacitor, a resistor, or an interconnection over the dielectric platform. 
     
     
       16. The method of  claim 11 , wherein etching the silicon substrate to form the plurality of sidewalls comprises etching the silicon substrate to form a plurality of openings, wherein the plurality of sidewalls are sidewalls of the plurality of openings. 
     
     
       17. The method of  claim 16 , further comprising:
   forming a subsurface cavity beneath the plurality of openings; and        depositing a dielectric material in the plurality of openings to form a plurality of voids in the dielectric platform, wherein the plurality of voids occupy in excess of  40   %  of the total volume of the dielectric platform.     
     
     
       18. The method of  claim 17 , wherein depositing a dielectric material comprises depositing an oxide layer in the plurality of openings using a TEOS process. 
     
     
       19. The method of  claim 17 , further comprising planarizing the dielectric material so that a top surface of the dielectric platform is substantially coplanar with a top surface of the silicon substrate. 
     
     
       20. The method of  claim 19 , wherein planarizing comprises chemical- mechanical polishing the dielectric material.   
     
     
       21. A method of forming a dielectric platform in a silicon substrate, wherein forming the dielectric platform comprises:
   etching the silicon substrate to form a plurality of sidewalls having portions of the silicon substrate between the plurality of sidewalls, wherein the plurality of sidewalls extend from a surface of the silicon substrate into the silicon substrate a distance of at least about three microns and wherein each of the plurality of sidewalls is curved; and        oxidizing the sidewalls to convert substantially all of the portions of the silicon substrate between the sidewalls to silicon dioxide.     
     
     
       22. The method of  claim 21 , wherein oxidizing the sidewalls includes oxidizing the sidewalls so that the dielectric constant of the dielectric platform is less than the dielectric constant of silicon dioxide. 
     
     
       23. The method of  claim 21 , wherein etching the silicon substrate to form the plurality of sidewalls comprises etching the silicon substrate to form a plurality of openings isolated from each other, wherein the plurality of sidewalls are sidewalls of the plurality of openings. 
     
     
       24. The method of  claim 23 , further comprising depositing a dielectric material in the plurality of openings to seal the plurality of openings. 
     
     
       25. The method of  claim 24 , wherein a thickness of the portions of the silicon substrate between the plurality of sidewalls is between  0 . 1  to  0 . 4  [less than about one] micron and wherein depositing a dielectric material comprises depositing an oxide layer in the plurality of openings using a TEOS process.