S-band low-noise amplifier with self-adjusting bias for improved power consumption and dynamic range in a mobile environment

Abstract

A discrete low-noise amplifier designed to operate in a mobile wireless environment uses two cascaded GaAs FETs to achieve 25 dB gain and 0.9 dB noise figure at 2.5 GHz. Active bias control circuitry responsive to monitored amplifier output power automatically and continuously adjusts the drain-source currents, and the load lines, of the cascaded FETs to (i) maintain power consumption at 33 milliwatts in nominal small-signal conditions, and to (ii) provide an elevated input third-order intermodulation intercept point (IP3) and a reduced noise figure during the presence of jamming. A 15 dB improvement in the input IP3 is achieved in large-signal operation. Amplifier operation is supported by an a.c. power detector of enhanced sensitivity and responsiveness because of un-grounded operation.

1. A method of operating an amplifier, which amplifier has an load line,
 to emulate the property of a class AB amplifier where increasing amplifier input current raises the d.c. bias of the amplifier and increases amplifier output current,  
 nonetheless that the amplifier will never enter class AB operation and will always operate in class A, the method of operating an amplifier always in class A nonetheless to producing more output current from more input current comprising: 
 monitoring the amplified output of the class A amplifier; and, in response to detecting an increase in the amplifier output,  
 dynamically biasing the load line of the amplifier to a higher d.c. bias point, causing the amplifier to consume more power and to produce a still larger amplified output signal, nonetheless to maintaining operation of the amplifier always in class A.  
 
 
     
     
       2. The class A amplifier operating method according to  claim 1  used on a class A amplifier serving as an initial low noise radio signal amplifier in a wireless communication system;
 wherein an increase in amplifier output signal is indicative of a presence of a strong jammer component in the amplifier input signal, so that moving the load line of the amplifier will cause the amplifier to draw more current beneficially decreasing a noise figure while increasing gain of the amplifier, and causing the amplifier to reach a new steady state with higher power and improved linearity;  
 wherein when no increase in amplifier output signal is detected, indicative that no strong jammer component is present within the amplifier input signal, then neither the d.c. bias, nor the load line, will be raised, and the amplifier will operate quiescently, conserving power.  
 
     
     
       3. An amplifier comprising:
 at least one Field Effect Transistor (FET) receiving at its gate an input signal from an external source and amplifying this input signal in accordance with its drain-source bias voltage V DS  to produce at its drain an amplified output signal;  
 a power detector circuit monitoring the amplified output signal to produce a detected-power voltage signal V DD ; and  
 a dynamic bias control circuit comparing the detected-power signal V DD  to the drain-source bias voltage V DS  to vary a gate-to-source voltage bias V GS  of the input signal, actively moving a load line of the FET so as to cause the FET to consume more power when the amplified output signal is large;  
 wherein when the amplified output signal is large because of a presence of a strong jammer component of the input signal, then the moved load line of the at least one FET will cause the FET to draw more current decreasing noise figure while increasing gain, and will cause the amplifier of which the at least one FET forms a part to reach a new steady state with higher power and improved linearity;  
 wherein, however, when no strong jammer component of the input signal is present, and when the amplified output signal is correspondingly not large, then the FET, and the amplifier of which it forms a part, will conserve power;  
 wherein a self-adjusting bias of the at least one FET results in improved power consumption and improved dynamic range in an environment where exists occasional strong jammer signals.  
 
     
     
       4. The amplifier according to  claim 3  wherein the at least one Field Effect Transistor (FET) comprises:
 two cascaded FETs.  
 
     
     
       5. The amplifier according to  claim 4  wherein the each of the two cascaded FETS comprises:
 a GaS FET.  
 
     
     
       6. The amplifier according to  claim 4  wherein a first, input, one of the two cascaded FETs comprises:
 a low-noise PHEMT; and wherein a second, output, one of the two cascaded FETs comprises: 
 a hetero-junction FET.  
 
 
     
     
       7. The amplifier according to  claim 3  wherein the dynamic bias control circuit comprises:
 two operational amplifiers each varying a gate-to-source voltage bias V GS  of an associated FET.  
 
     
     
       8. The amplifier according to  claim 3  wherein the power detector circuit comprises:
 a resistor R; and  
 a first diode D 1  series connected to form a diode-limited resistive divider.  
 
     
     
       9. The amplifier according to  claim 8  wherein the diode-limited resistive divider and first diode D 1  are both temperature compensated by a second diode D 2 . 
     
     
       10. The amplifier according to  claim 3  wherein the power detector circuit is temperature compensated. 
     
     
       11. The amplifier according to  claim 3  operational in S band. 
     
     
       12. A circuit for detecting a peak power of an a.c. signal, the peak power detector circuit comprising:
 a resistive voltage divider, located between a voltage source and ground, producing a reference voltage signal;  
 a diode connecting at its cathode to both the a.c. signal and to the reference voltage signal; and  
 an envelope detector connected both to the anode of the diode and to the reference voltage;  
 wherein output of the detector circuit appears across the envelope detector;  
 wherein when the a.c. signal is zero then the detector circuit output is equal to the reference voltage;  
 wherein when the a.c. signal is not zero then the detector circuit output is equal to a sum of (i) the reference voltage, and (ii) a voltage of an envelope of the a.c. signal, which voltage of the envelope of the a.c. signal is equivalent to the power of the a.c. signal.  
 
     
     
       13. A method of operating an amplifier, comprising:
   monitoring an output of the amplifier, wherein the amplifier is a class A amplifier;        in response to detecting an increase in the output of the amplifier, dynamically biasing the amplifier to further increase the output of the amplifier while continuing to operate the amplifier as a class A amplifier,        wherein the dynamically biasing causes the amplifier to draw more current.     
     
     
       14. The method of  claim 13 , wherein the method is performed in a wireless communication system, and wherein the increase in the output of the amplifier is indicative of jamming of an output signal of the amplifier. 
     
     
       15. An amplifier comprising:
   one or more active devices configured to amplify an input signal in accordance with a bias signal, producing an amplified output signal;        a power detector circuit configured to monitor the amplified output signal to produce a detected power signal; and        a dynamic bias control circuit configured to compare the detected power signal and the bias signal to produce a difference signal, wherein said dynamic bias control circuit is further configured to adjust said bias signal by biasing the one or more active devices until the difference signal is substantially zero.     
     
     
       16. The amplifier of  claim 15 , wherein the one or more active devices include two cascaded field effect transistors ( FETs ). 
     
     
       17. The amplifier of  claim 16 , wherein the two cascaded FETS are GaS FETs. 
     
     
       18. The amplifier of  claim 16  wherein the two cascaded FETs include an input FET and an output FET, wherein the input FET is a low- noise Pseudomorphic High Electron Mobility transistor  ( PHEMT ). 
     
     
       19. The amplifier of  claim 18 , wherein the output FET is a hetero- junction FET.   
     
     
       20. The amplifier of  claim 16 , wherein said two cascaded FETs include an input FET and an output FET, wherein the dynamic bias control circuit includes a first operational amplifier with an output coupled to a gate of said input FET, wherein said dynamic bias control circuit further includes a second operational amplifier with an output coupled to a gate of said output FET. 
     
     
       21. The amplifier of  claim 15 , wherein the power detector circuit includes:
   a reference voltage circuit configured to produce a reference voltage at a first node;        a first diode coupled between said first node and a second node; and        an envelope detector coupled to said second node.     
     
     
       22. The amplifier of  claim 21 , further comprising a second diode coupled to said envelope detector and said first node, wherein said second diode is configured to perform temperature compensation. 
     
     
       23. The amplifier of  claim 15 , wherein the power detector circuit is temperature compensated. 
     
     
       24. The amplifier of  claim 15 , wherein said amplifier is operational in S band. 
     
     
       25. A detection circuit for detecting a peak power of an a.c. signal in a first circuit, the circuit comprising:
   a reference voltage circuit coupled to said first circuit at a first node, wherein said reference voltage circuit is configured to produce a reference voltage at said first node;        a first diode coupled to said first node and a second node; and        an envelope detector circuit coupled to said second node and said first node, wherein said envelope detector circuit is configured to produce an output that corresponds to the sum of  ( i )  the reference voltage and  ( ii )  a voltage of an envelope of the a.c. signal, wherein the voltage of the envelope of the a.c. signal corresponds to the power of the a.c. signal.     
     
     
       26. The detection circuit of  claim 25 , wherein the envelope detector circuit is coupled to said first node via a second diode. 
     
     
       27. A device comprising:
   first means for amplifying an input signal to produce an output signal;        second means for monitoring the output signal to produce a first signal indicative of the power of said output signal; and        third means for varying a bias signal in accordance with a difference between the first signal and the bias signal,        wherein said third means is configured to vary the bias signal until the difference between the first signal and the bias signal is substantially zero.     
     
     
       28. The device as recited in  claim 27 , wherein the device is a mobile communications system. 
     
     
       29. The device as recited in  claim 28 , wherein the device is a mobile telephone. 
     
     
       30. An amplifier comprising:
   an amplification circuit having an input transistor and an output transistor cascaded together, wherein the amplification circuit further includes an input node and an output node;        a detector circuit coupled to the output node, wherein the detector circuit is configured to produce a first signal indicative of the power of an output signal on the output node;        a biasing circuit including a first operational amplifier having an output operatively coupled to a gate terminal of the input transistor and a second operational amplifier having an output operatively coupled to a gate terminal of the output transistor, wherein the biasing circuit is configured to vary a bias signal on the gate terminals of the input and output transistors in accordance with a difference between the first signal and the bias signal.     
     
     
       31. The amplifier as recited in  claim 30 , wherein the biasing circuit is configured to vary the bias signal until the difference is substantially zero. 
     
     
       32. The amplifier as recited in  claim 30 , wherein the detector circuit comprises a resistive voltage divider network, an envelope detector, a first diode, and a second diode. 
     
     
       33. The amplifier as recited in  claim 32 , wherein a cathode of the first diode is coupled to a first node, and wherein the first node is operatively coupled to the output node via an AC path circuit comprising a resistor and a capacitor coupled in series between the first node and the output node. 
     
     
       34. The amplifier as recited in  claim 33 , wherein an anode of the second diode is coupled to the first node, wherein the second diode is configured to perform temperature compensation. 
     
     
       35. The amplifier as recited in  claim 33 , wherein the resistive voltage divider network is configured to produce a reference voltage on the first node. 
     
     
       36. The amplifier as recited in  claim 35 , wherein, when an AC amplitude of the output signal is approximately zero, a voltage of the first signal is substantially equal to the reference voltage. 
     
     
       37. The amplifier as recited in  claim 35 , wherein, when an AC amplitude of the output signal is not substantially zero, a voltage of the first signal is approximately equal to the sum of the reference voltage and a voltage of the output signal. 
     
     
       38. The amplifier as recited in  claim 30 , wherein each of the first and second operational amplifiers includes a first and a second input, and wherein a first input of each of the first and second operational amplifiers is coupled to receive the first signal. 
     
     
       39. The amplifier as recited in  claim 38 , wherein the second input of the first operational amplifier is operatively coupled to a drain terminal of the input transistor and wherein the second input of the second operational amplifier is operatively coupled to a drain terminal of the output transistor. 
     
     
       40. The amplifier as recited in  claim 39 , wherein the first operational amplifier is configured to compare a voltage of the first signal to a drain- source voltage of the input transistor, and wherein the second operational amplifier is configured to compare the voltage of the first signal to a drain - source voltage of the output transistor.   
     
     
       41. The amplifier as recited in  claim 30 , wherein the first and second transistors are gallium arsenide ( GaAs )  transistors.   
     
     
       42. The amplifier as recited in  claim 41 , wherein the input transistor is a low- noise Pseudomorphic High Electron Mobility transistor  ( PHEMT )  and wherein the output transistor is a hetero - junction field effect transistor  ( FET ). 
     
     
       43. The amplifier as recited in  claim 30 , wherein the amplifier is a low noise amplifier ( LNA ). 
     
     
       44. The amplifier as recited in  claim 30 , wherein the amplification circuit is a class A amplifier having an input current and an output current, and wherein the amplification circuit is configured such that increasing the input current raises a D.C. bias of the amplification circuit and causes a corresponding increase in the output current. 
     
     
       45. An amplifier comprising:
   one or more active devices configured to amplify an input signal in accordance with a bias signal to produce an amplified output signal;        a detector circuit configured to monitor the amplified output signal to produce a first signal; and        a dynamic bias control circuit configured to adjust the bias signal in response to any difference between the first signal and the bias signal,        wherein the one or more active devices include two cascaded field effect transistors  ( FETs ) , and wherein said two cascaded FETs include an input FET and an output FET, wherein the dynamic bias control circuit includes a first operational amplifier with an output coupled to a gate of said input FET, wherein said dynamic bias control circuit further includes a second operational amplifier with an output coupled to a gate of said output FET.     
     
     
       46. The amplifier as recited in  claim 45 , wherein the two cascaded FETs are GaAs FETs. 
     
     
       47. The amplifier as recited in  claim 46 , wherein the two cascaded FETs include an input FET and an output FET, wherein the input FET is a low- noise Pseudomorphic High Electron Mobility transistor  ( PHEMT ). 
     
     
       48. The amplifier as recited in  claim 47 , wherein the output FET is a hetero- junction FET.   
     
     
       49. The amplifier as recited in  claim 45 , wherein the detector circuit includes:
   a reference voltage circuit configured to produce a reference voltage at a first node;        a first diode coupled between said first node and a second node; and        an envelope detector coupled to said second node.     
     
     
       50. The amplifier as recited in  claim 49 , further comprising a second diode coupled to said envelope detector and said first node, wherein said second diode is configured to perform temperature compensation. 
     
     
       51. The amplifier as recited in  claim 45 , wherein the detector circuit is temperature compensated. 
     
     
       52. The amplifier as recited in  claim 45 , wherein the detector circuit is ungrounded. 
     
     
       53. The amplifier as recited in  claim 45 , wherein said amplifier is operational in S band. 
     
     
       54. A method of operating an amplifier circuit, the method comprising:
   receiving an input signal;        amplifying the input signal to produce an output signal;        producing a first signal indicative of power of the output signal;        varying a bias signal in accordance with a difference between the first signal and the bias signal; and        operating the amplifier circuit as a class A amplifier, wherein the amplifier circuit is configured such that increasing an input current causes a corresponding increase in a DC bias of one or more active devices in the amplifier circuit.     
     
     
       55. The method as recited in  claim 54 , wherein said receiving occurs during jamming of said input signal. 
     
     
       56. The method as recited in  claim 54 , wherein said varying a bias signal causes the amplifier circuit to conserve power in small- signal conditions and to consume relatively more power when an amplitude of the output signal is large.   
     
     
       57. The method as recited in  claim 56 , wherein the output signal is large in the presence of jamming. 
     
     
       58. The method as recited in  claim 54 , wherein said producing includes providing a reference voltage, wherein the reference voltage is provided without a direct reference to a ground. 
     
     
       59. The method as recited in  claim 58 , wherein the first signal is the sum of the reference voltage and a voltage of the output signal. 
     
     
       60. The method as recited in  claim 54 , further comprising comparing a voltage of the first signal to a voltage on a drain terminal of a transistor in an amplification section of the amplifier circuit. 
     
     
       61. The method as recited in  claim 60  further comprising driving the bias signal to a gate terminal of the transistor based on an output voltage produced from said comparing. 
     
     
       62. A device comprising:
   a low - noise amplifier configured to conserve power during small - signal conditions and to increase amplification gain and reduce distortion during input signal jamming,        wherein the low - noise amplifier includes an amplification circuit having an input transistor cascaded with an output transistor, wherein the amplification circuit further includes an input node and an output node,        wherein the low - noise amplifier includes a detector circuit coupled to the output node, wherein the detector circuit is configured to monitor an output signal on the output node and to produce a first signal indicative of the power of said output signal, and        wherein the low - noise amplifier includes a biasing circuit having a first operational amplifier with an output operatively coupled to a gate terminal of the input transistor and a second operational amplifier having an output operatively coupled to a gate terminal of the output transistor, wherein the biasing circuit is configured to vary a bias signal on the gate terminals of the input and output transistors in accordance with a difference between the first signal and the bias signal until the difference is substantially zero.     
     
     
       63. The device as recited in  claim 62 , wherein the device is a telephone. 
     
     
       64. A communications device comprising:
   an amplifier including one or more active devices configured to amplify an input signal in accordance with a bias signal to produce an amplified output signal;        a detector circuit configured to produce a first signal indicative of the power of the amplified output signal; and        a dynamic bias control circuit configured to adjust the bias signal in response to any difference between the first signal and the bias signal,        wherein the amplifier includes an amplification circuit having an input transistor cascaded with an output transistor, wherein the amplification circuit further includes an input node and an output node,        wherein the amplifier includes a detector circuit coupled to the output node, wherein the detector circuit is configured to produce a first signal indicative of the power of an output signal on the output node, and        wherein the amplifier includes a biasing circuit including a first operational amplifier having an output operatively coupled to a gate terminal of the input transistor and a second operational amplifier having an output operatively coupled to a gate terminal of the output transistor,        wherein the biasing circuit is configured to vary a bias signal on the gate terminals of the input and output transistors in accordance with a difference between the first signal and the bias signal until the difference is substantially zero.     
     
     
       65. The communications device as recited in  claim 64 , wherein the detector circuit is ungrounded. 
     
     
       66. The communications device as recited in  claim 64 , wherein the communications device is a telephone. 
     
     
       67. A communications device comprising:
   an amplifier configured to automatically increase power consumption in the presence of jamming, and further configured to exhibit low power consumption during small - signal conditions,        wherein the amplifier includes an amplification circuit having an input transistor cascaded with an output transistor, wherein the amplification circuit further includes an input node and an output node,        wherein the amplifier includes a detector circuit coupled to the output node, wherein the detector circuit is configured to produce a first signal indicative of the power of an output signal on the output node, and        wherein the amplifier includes a biasing circuit including a first operational amplifier having an output operatively coupled to a gate terminal of the input transistor and a second operational amplifier having an output operatively coupled to a gate terminal of the output transistor,        wherein the biasing circuit is configured to vary a bias signal on the gate terminals of the input and output transistors in accordance with a difference between the first signal and the bias signal until the difference is substantially zero.     
     
     
       68. The communications device as recited in  claim 67 , wherein the detector circuit is ungrounded. 
     
     
       69. The communications device as recited in  claim 67 , wherein the amplifier is a low- noise amplifier.   
     
     
       70. The communications device as recited in  claim 67 , wherein the communications device is a telephone. 
     
     
       71. A method of operating an amplifier circuit configured to receive an input signal, the method comprising:
   during small - signal conditions for said input signal, conserving amplifier power; and        in response to the presence of jamming of said input signal, consuming relatively more power than during said small - signal conditions;        operating the amplifier circuit as a class A amplifier, wherein the amplifier circuit is configured such that increasing an input current causes a corresponding increase in a DC bias of one or more active devices in the amplifier circuit.     
     
     
       72. The method as recited in  claim 71 , wherein the method further includes:
   receiving the input signal;        amplifying the input signal to produce an output signal;        producing a first signal indicative of power of the output signal; and        varying a bias signal in accordance with a difference between the first signal and the bias signal.     
     
     
       73. A power detection circuit, comprising:
   a reference voltage circuit configured to produce a reference voltage;        an envelope detection circuit coupled to said reference voltage circuit and configured to produce a first output signal indicative of the power of an AC input signal to the power detection circuit;        wherein said first output signal is produced without direct reference to ground,        further comprising a diode coupled between said envelope detection circuit and a node coupled to said AC input signal.     
     
     
       74. The power detection circuit as recited in  claim 73 , wherein said envelope detection circuit is an RC circuit. 
     
     
       75. The power detection circuit as recited in  claim 74 , further comprising a means for performing temperature compensation. 
     
     
       76. The power detection circuit as recited in  claim 73 , wherein said envelope detection circuit is coupled to said reference voltage circuit via a diode.