Frequency-stabilized transceiver configuration

Abstract

A transceiver configuration has an integrated circuit (IC) with an A/D and/or D/A converter, a VCO with a reference oscillator, which provides a sampling clock for the A/D and/or D/A converter, and a digital data processing circuit. The IC is connected to a radio-frequency section, the frequency converter stage of which is operated with a beat frequency derived from the controllable oscillator frequency f oz . A capacitive resonant element of the reference oscillator is disposed outside of the IC.

1. A transceiver configuration for a communication terminal, comprising:
 an A/D converter outputting a first digital data signal;  
 a D/A converter;  
 a controllable oscillator circuit connected to said A/D converter and to said D/A converter, said controllable oscillator circuit having a reference oscillator with an oscillating crystal as a resonator and outputs a sampling clock received by said A/D converter and said D/A converter;  
 a digital data processing circuit connected to said A/D converter and to said D/A converter and receives the first digital data signal output by said A/D converter and processes it further and outputs a second digital data signal to said D/A converter;  
 said A/D converter, said D/A converter, said data processing circuit and said controllable oscillator circuit, apart from said oscillating crystal of said reference oscillator, being constructed as a monolithically integrated circuit so that of said controllable oscillator circuit, only said oscillating crystal is implemented as an external component; and  
 a frequency section being at least one of a radio-frequency section and an intermediate-frequency section connected to said A/D converter, to said D/A converter and to said controllable oscillator circuit, said frequency section having a frequency converter stage operating with a beat frequency derived from said controllable oscillator circuit.  
 
     
     
       2. The transceiver configuration according to  claim 1 , wherein said digital data processing circuit has a digital filter and a digital modulator. 
     
     
       3. The transceiver configuration according to  claim 1 , wherein said digital data processing circuit has a channel estimator. 
     
     
       4. The transceiver configuration according to  claim 3 , including a data detector connected to said channel estimator. 
     
     
       5. A transceiver configuration, comprising:
   an A/D converter;        a D/A converter;        an oscillator circuit configured to provide a sampling clock that is received by the A/D converter and the D/A converter;        a digital data processing circuit that receives a first digital data signal from the A/D converter and provides a second digital data signal to the D/A converter; and        a frequency section coupled to the A/D converter and the D/A converter, wherein the frequency section comprises a frequency converter stage that operates with a beat frequency derived from the sampling clock.     
     
     
       6. The transceiver of  claim 5 , wherein the reference oscillator comprises an oscillating crystal. 
     
     
       7. The transceiver of  claim 6 , wherein the A/D converter, the D/A converter and the oscillator circuit, apart from the oscillating crystal, are constructed as a monolithic integrated circuit. 
     
     
       8. A transceiver, comprising:
   an A/D converter;        a D/A converter;        an oscillator circuit configured to provide a clock signal to the A/D converter and the D/A converter, wherein the clock signal is corrected by comparing a control input signal to a phase difference between a reference oscillator signal frequency and a clock signal frequency; and        a frequency section configured to communicate with the A/D converter and the D/A converter and operate at a frequency derived from the clock signal, wherein the frequency section provides the control input signal to the oscillator circuit.     
     
     
       9. The transceiver of  claim 8 , wherein the control input signal is derived from a frequency correction burst signal that is received by the frequency section. 
     
     
       10. The transceiver of  claim 8 , wherein the oscillator circuit comprises an oscillating crystal. 
     
     
       11. The transceiver of  claim 10 , wherein the D/A converter, the D/A converter and the oscillator circuit, apart from the oscillating crystal, are constructed as a monolithic integrated circuit, and wherein the oscillating crystal is implemented as an external component. 
     
     
       12. A receiver, comprising:
   an A/D converter;        an oscillator circuit configured to provide a sampling clock that is received by the A/D converter;        a digital data processing circuit configured to receive a digital data signal from the A/D converter; and        a frequency section coupled to the A/D converter, wherein the frequency section comprises a frequency converter stage that operates with a beat frequency derived from the sampling clock.     
     
     
       13. The receiver of  claim 12 , wherein the oscillator circuit comprises an oscillating crystal. 
     
     
       14. The receiver of  claim 13 , wherein the A/D converter and the oscillator circuit, apart from the oscillating crystal, are constructed as a monolithic integrated circuit. 
     
     
       15. A transmitter, comprising:
   a D/A converter;        an oscillator circuit configured to provide a sampling clock that is received by the D/A converter;        a digital data processing circuit that provides a digital data signal to the D/A converter; and        a frequency section coupled to the D/A converter, wherein the frequency section comprises a frequency converter stage that operates with a beat frequency derived from the sampling clock.     
     
     
       16. The transmitter of  claim 15 , wherein the oscillator circuit comprises an oscillating crystal. 
     
     
       17. The transmitter of  claim 16 , wherein the D/A converter and the oscillator circuit, apart from the oscillating crystal, are constructed as a monolithic integrated circuit. 
     
     
       18. The transmitter of  claim 15 , wherein the oscillator circuit is configured to correct the sampling clock by comparing a control input signal to a phase difference between a reference oscillator signal frequency and a sampling clock frequency. 
     
     
       19. The transmitter of  claim 18 , wherein the control input signal is derived from a frequency correction burst signal that is received by the frequency section. 
     
     
       20. A method of operating a receiver; comprising;
   correcting a clock signal by comparing a control input signal to a phase difference between a reference oscillator signal frequency that is derived from a crystal oscillator and a frequency of the clock signal;        converting a received signal into an analog signal using a beat frequency derived from the clock signal; and        converting the analog signal into a digital data signal using the frequency of the clock signal as a sampling frequency.     
     
     
       21. The method of  claim 20 , wherein comparing the control input signal to the phase difference comprises subtracting either the control input signal from the phase difference or the phase difference from the control input signal. 
     
     
       22. The method of  claim 20 , further comprising:
   receiving a frequency correction signal; and        converting the frequency correction signal into the control input signal.     
     
     
       23. A method of operating a transmitter, comprising:
   correcting a clock signal by comparing a control input signal to a phase difference between a reference oscillator signal frequency that is derived from a crystal oscillator and a frequency of the clock signal;        converting a digital data signal into an analog signal using the frequency of the clock signal as a sampling frequency; and        converting the analog signal into a transmit signal using a beat frequency derived from the clock signal.     
     
     
       24. The method of  claim 23 , wherein comparing the control input signal to the phase difference comprises subtracting either the control input signal from the phase difference or the phase difference from the control input signal. 
     
     
       25. The method of  claim 23 , further comprising:
   receiving a frequency correction signal; and        converting the frequency correction signal into the control input signal.     
     
     
       26. A method of operating a transceiver, comprising:
   correcting a clock signal by determining a phase difference between a reference oscillator signal frequency that is derived from a crystal oscillator and a frequency of the clock signal;        converting a received signal into a first analog signal using a beat frequency derived from the clock signal;        converting the first analog signal into a first digital data signal using the frequency of the clock signal as a sampling frequency;        converting a second digital data signal into a second analog signal using the frequency of the clock signal as the sampling frequency; and        converting the second analog signal into a transmit signal using the beat frequency that is derived from the clock signal.     
     
     
       27. The method of  claim 26 , further comprising:
   determining a control error by comparing a control input signal to the phase difference; and        adjusting the frequency of the clock signal based on the control error.     
     
     
       28. The method of  claim 27 , wherein comparing the control input signal to the phase difference comprises subtracting either the control input signal from the phase difference or the phase difference from the control input signal. 
     
     
       29. The method of  claim 27 , further comprising:
   receiving a frequency correction signal; and        converting the frequency correction signal into the control input signal.