Timing signal generation for charge-coupled device

Abstract

A method of generating timing signals for a charge-coupled device. A plurality of input timing signals produced by an application specific integrated circuit according to a system clock is transmitted to the charge-coupled device. The programmable timing signals for the charge-coupled device are produced by determining the position of each cycle for these input timing signal, adjusting each cycle of the input timing signals in each system clock cycle and downloading their relationship into the application specific integrated circuit by programming.

1. A method of generating timing signals for a charge-coupled device, comprising the steps of :
 determining cycles of each input timing signal sent to control the charge-coupled device; and  
 adjusting a position of each cycle of the input timing signals according to each cycle of a system clock;  
 wherein each duty  cycle of the input timing signal for the charge-coupled device determines each duty  cycle of a shift register timing signal of the charge-coupled device, and for a charge signal that needs to be sampled by the charge-coupled device, duration of the cycle of the shift register timing signal corresponding to the charge signal is extended, and for another charge signal that needs to be discarded by the charge-coupled device, duration of the cycle of the shift register timing signal corresponding to the charge signal is shortened.  
 
     
     
       2. The method of  claim 1 , wherein the cycle of the shift register timing signal corresponding to the to-be-sampled charge signal is adjusted through changing cycle duration of a positioning signal so that an analogue  analog front-end processor inside an application specific integrated circuit can receive a stable positioning voltage. 
     
     
       3. The method of  claim 1 , wherein the cycle of the shift register timing signal corresponding to the to-be-discarded charge signal is adjusted through changing cycle duration of a reset signal so that an analogue front-end processor inside an application specific integrated circuit can produce a reset voltage for flushing away the to-be-discarded charge signal. 
     
     
       4. The method of  claim 1 , wherein input timing signals produced by an application specific integrated circuit according to a  the system clock are transmitted to the charge-coupled device. 
     
     
       5. The method of  claim 4 , wherein a  the position of each cycle of the input timing signals relative to each cycle of the system clock is programmed into the application specific integrated circuit. 
     
     
       6. A method of generating timing signals for controlling a charge-coupled device, comprising the steps of :
 determining each cycle of a shift register signal, a reset signal and a positioning signal for the charge-coupled device;  
 in each cycle of a system clock, lengthening the cycle of the shift register signal corresponding to a charge signal that needs to be sampled by the charge-coupled device; , and shortening the cycle of the shift register signal corresponding to another charge signal that needs to be discarded by the charge-coupled device;  
 in each cycle of the system clock and each cycle of the shift register signal, adjusting cycle duration of the positioning signal so that an analogue  analog front-end processor can obtain a stable voltage; and  
 in each cycle of the system clock and each cycle of the shift register signal that corresponds to the to-be-discarded charge signal, adjusting cycle duration of the reset signal so that the analogue  analog front-end processor generates a reset signal to flush away the to-be-discarded charge signal.  
 
     
     
       7. The method of  claim 6 , wherein input timing signals produced by an application specific integrated circuit according to a  the system clock are transmitted to the charge-coupled device. 
     
     
       8. The method of  claim 7 , wherein a position of each cycle of the shift register signal, the positioning signal and the reset signal relative to each cycle of the system clock is programmed into the application specific integrated circuit. 
     
     
       9. An apparatus, comprising:
   a charge - coupled device including a shift register; and        a timing signal generation circuit coupled to the charge - coupled device, wherein the timing signal generation circuit is configured to generate a shift register clock signal for driving the charge - coupled device, wherein the shift register clock signal has a first cycle time and a second cycle time, wherein the second cycle time is shorter in duration than the first cycle time, and wherein the first cycle time and the second cycle time are associated with a single scanning period.     
     
     
       10. The apparatus of  claim 9 , wherein the charge- coupled device is configured to output a voltage during the first cycle time and, wherein the voltage corresponds, at least in part, to a charge signal sampled by the charge - coupled device.   
     
     
       11. The apparatus of  claim 9 , wherein the charge- coupled device is configured to output a reset voltage during the second cycle time.   
     
     
       12. The apparatus of  claim 9 , wherein the charge- coupled device is configured to not output a voltage during the second cycle time and, wherein the voltage corresponds, at least in part, to a charge signal sampled by the charge - coupled device.   
     
     
       13. A method, comprising:
   applying a first timing signal during a horizontal scanning period for a first period of time to cause a scanner sensor to output a voltage corresponding, at least in part, to a first sampled charge signal; and        applying the first timing signal for a second period of time during the horizontal scanning period to cause the scanner sensor to not output a voltage corresponding, at least in part, to a second sampled charge signal, wherein the second period of time is shorter in duration than the first period of time.     
     
     
       14. The method of  claim 13 , wherein the scanner sensor is a charge- coupled device.   
     
     
       15. An analog front- end processor for use in combination with a charge - coupled device  ( CCD ) , the analog front - end processor comprising:      a system clock input configured to receive a system clock signal;        a digital output configured to provide digital data in response to analog signals received from the CCD;        clocking signal outputs configured to provide shift register timing signals to drive the CCD, wherein the shift register timing signals are synchronized to the system clock signal, and wherein each timing signal has a period equal to an integer number of cycles of the system clock signal;        means for determining a selected output image resolution;        an analog input voltage sampling circuit configured to sample an analog charge signal input from the CCD; and        means responsive to the selected output image resolution for, if the selected output image resolution is a low resolution relative to a predetermined image resolution:      reducing a number of system clock cycles of the shift register timing signals to increase image scanning speed; and        lengthening a duty cycle of the analog input voltage sampling circuit to ensure that the analog charge signal sampled by the analog input voltage sampling circuit is accurate.       
     
     
       16. The analog front- end processor of    claim 15   , wherein the means for lengthening a duty cycle comprises means for discarding or not sampling the analog charge signal during selected clock cycles.   
     
     
       17. The analog front- end processor of    claim 16   , wherein the analog front - end processor generates a reset voltage to flush out the to - be - discarded analog charge signal.   
     
     
       18. The analog front- end processor of    claim 15   , wherein the analog front - end processor generates a positioning voltage for use as a reference voltage to determine pixel brightness value, and wherein the means for lengthening a duty cycle comprises means for increasing a time period from generating the positioning voltage to sampling the analog charge signal so that the positioning voltage is stable at a charge voltage sample time even though the number of system clock cycles of the shift register timing signals is reduced.   
     
     
       19. The analog front- end processor of    claim 18   , wherein the means for increasing a time period comprises means for adjusting a duration of a positioning signal in response to both the system clock signal and a first cycle of the shift register timing signals.   
     
     
       20. The analog front- end processor of    claim 19   , wherein the positioning signal is held unchanged over subsequent cycles of the shift register timing signals until a new low - resolution sampling cycle begins.   
     
     
       21. The analog front- end processor of    claim 19   , wherein the analog front - end processor is formed together with a digital processing circuit in a common semiconductor integrated circuit, and wherein the digital processing circuit is configured to receive the digital data output from the analog front - end processor in response to the sampled analog charge signal received from the CCD.