Bus clock controlling apparatus and method

Abstract

The present invention relates to an apparatus and method for throttling a clock of a bus used for data exchange between devices in a computer such as a portable computer or notebook. Methods according to the invention can set a throttle rate of a clock to a predetermined initial value, detect a current remaining battery capacity or a current load to the CPU, and adjust the set throttle rate to a prescribed or calculated value according to the detected remaining battery capacity or the CPU load. Thus, power consumption is reduced, and, in the case of a battery-powered computer, battery life and operating time are extended.

1. A bus clock controlling method in a computer, comprising:
 setting a throttle rate of a clock to a predetermined initial value, the clock configured to set a speed of a data bus connected between a CPU and a controlling device;  
 detecting a remaining battery capacity if a present power source is at least one battery; and  
 adjusting the set throttle rate by the controlling device according to the detected remaining battery capacity, wherein the set throttle rate is adjusted when the controlling device is providing the clock to the data bus between the CPU and the controlling device.  
 
     
     
       2. The method set forth in  claim 1 , wherein said adjusting step increases the set throttle rate as the detected remaining battery capacity decreases. 
     
     
       3. The method set forth in  claim 1 , wherein said adjusting step selects one value appropriate to the detected remaining battery capacity among a plurality of throttle rates preset in reverse proportion to different remaining battery capacities. 
     
     
       4. The method set forth in  claim 1 , wherein said controlling device is a bridge controller in a computer, wherein a second clock is provided to the controlling device and the CPU, and wherein the throttle rate of the clock is set independently of the second clock, and wherein the clock has a different value than the second clock. 
     
     
       5. The method of  claim 1 , comprising:
 generating the clock for the CPU and the controlling device; and  
 determining the throttle rate using a second controlling device according to the remaining battery capacity and outputting the throttle rate to the controlling device, wherein said second controlling device outputs the throttle rate in the form of a pulse signal whose duty cycle varies in accordance with the detected remaining battery capacity, and wherein the controlling device includes a throttle controller providing the data bus with the throttled clock only when the pulse signal is in a specific state.  
 
     
     
       6. A bus clock controlling method in a computer, comprising:
 setting a throttle rate of a clock to a predetermined initial value, the clock configured to set a speed of a data bus connected between a CPU and a controlling device;  
 detecting a present load of the CPU; and  
 adjusting the set throttle rate in reverse relation to  based on the detected present CPU load by the controlling device  by the controlling device, wherein the set throttle rate is adjusted when the controlling device is providing the clock to the data bus between the CPU and the controlling device.  
 
     
     
       7. The method set forth in  claim 6 , wherein said adjusting step is conducted only when a present power source is at least one battery, wherein a second clock is provided to the controlling device and the CPU, and wherein the throttle rate of the clock is set independently of the second clock, and wherein the clock has a different value than the second clock. 
     
     
       8. The method set forth in  claim 6 , wherein said adjusting step includes selecting a new throttle rate appropriate to the detected CPU load from a plurality of throttle rates preset in reverse proportion to different CPU loads. 
     
     
       9. The method of  claim 6 , comprising:
 generating the clock for the CPU and the controlling device; and  
 determining the throttle rate using a second controller according to the remaining battery capacity and outputting the throttle rate to the controlling device, wherein said second controller outputs the throttle rate in the form of a pulse signal whose duty cycle varies in accordance with the present load of the CPU, and wherein the controlling device includes a throttle controller providing the data bus with the throttled clock only when the pulse signal is in a specific state.  
 
     
     
       10. A computer, comprising:
 a CPU that processes;  
 a first controller coupled to the CPU via a data bus, and configured to provide a throttled clock to the data bus according to a throttle rate;  
 a clock generator coupled to the CPU and the first controller, and configured to generate a clock for the CPU and the first controller;  
 a detector detecting a variable, wherein the variable is a remaining battery capacity or a load of the CPU; and  
 a second controller coupled to receive the detected variable, configured to determine  adjust the throttle rate according to the detected variable, and further configured to output the adjusted throttle rate to the first controller, wherein the throttled clock is configured to selectively have a different independent value than the clock supplied to the first controller and the clock supplied to the second controller.  
 
     
     
       11. The computer of  claim 10 , wherein said second controller outputs the throttle rate in the form of a pulse signal whose duty cycle varies in accordance with the detected variable, and wherein the first controller includes a throttle controller providing the data bus with the throttled clock only when the pulse signal is in a specific state. 
     
     
       12. The computer of  claim 10 , wherein said first controller is a bridge controller, and wherein said second controller determines the throttle rate in reverse proportion to the detected variable, wherein the bridge controller directly sets the throttled clock speed of the data bus. 
     
     
       13. The computer of  claim 10 , wherein the throttle rate increases as a value of the detected variable decreases. 
     
     
       14. The computer of  claim 10 , wherein the second controller comprises:
 at least one comparator coupled to receive the detected variable from the detector, configured to compare the detected variable to a plurality of predetermined values, and further configured to output a result of the corresponding plurality of comparisons; and  
 a host clock throttler coupled to receive the plurality of comparisons and a power mode signal, and configured to output the throttle rate to the first controller.  
 
     
     
       15. The computer of  claim 14 , wherein the at least one comparator comprises a remaining battery capacity comparator, and wherein the detected variable is the remaining battery capacity. 
     
     
       16. The computer of  claim 14 , wherein the at least one comparator comprises a CPU load comparator, and wherein the detected variable is the load of the CPU. 
     
     
       17. The computer of  claim 14 , wherein the at least one comparator comprises a remaining battery capacity comparator and a CPU load comparator. 
     
     
       18. A bus clock controlling method in a computer, comprising:
 setting a throttle rate of a clock to a predetermined initial value, the clock being used for a data bus to which both a CPU and a controlling device are connected;  
 detecting a remaining battery capacity or a load of the CPU if a present power source is a battery; and  
 adjusting the set throttle rate according to the detected remaining battery capacity and  or the detected CPU load, wherein a second clock is provided to the controlling device and the CPU, and wherein the throttle rate of the clock is set independently of the second clock, and wherein the clock has a different value than the second clock.  
 
     
     
       19. The method of  claim 18 , wherein a third clock is provided to the CPU, wherein the clock as a different value than the third clock. 
     
     
       20. A bus clock controlling method in a portable computer, comprising:
 setting a throttle rate of a clock to a predetermined initial value, the clock being used for a data bus connected between a controlling device and a selected one of a plurality of devices associated with the portable computer;  
 detecting a condition of a remaining battery or a CPU load of the portable computer if a present power source is a battery; and  
 adjusting the set throttle rate using the controlling device according to the detected condition, wherein the detected condition is within a range of values for the prescribed criteria, wherein a first clock is provided to the controlling device and a second clock is provided the CPU, and wherein the throttle rate of the clock is set independently of the first clock and the second clock, and wherein the clock has a different value than the first clock and the second clock.  
 
     
     
       21. The bus clock controlling method of  claim 20 , wherein the selected device is a peripheral device, and wherein the predetermined initial value is a smallest throttle rate, wherein the controlling device directly sets the clock during normal operations. 
     
     
       22. The bus clock controlling method of  claim 20 , wherein said adjusting step selects a rate corresponding to the detected condition among a plurality of prescribed throttle rates that each correspond to mutually exclusive sets of values of the detected condition within the range of values for the prescribed criteria. 
     
     
       23. The bus clock controlling method of  claim 22 , wherein each of the plurality of prescribed throttle rates increases as the detected condition decreases within the range. 
     
     
       24. A bus clock controlling method in a computer, comprising
 setting a throttle rate of a clock to a predetermined initial value, the clock configured to set a speed of a data bus to which both a controlling device and a peripheral device are connected;  
 detecting one member chosen from  of a present load of the CPU and a remaining battery capacity; and  
 adjusting the set throttle rate by the controlling device in reverse relation to  by the controlling device based on the detected one of the present CPU load and the remaining battery capacity, wherein the set throttle rate is adjusted when the controlling device is providing the clock to the data bus between the controlling device and the peripheral device.  
 
     
     
       25. The method of  claim 24 , comprising:
 generating the clock for the CPU and the controlling device; and  
 determining the throttle rate using a second controller according to the remaining battery capacity and outputting the throttle rate to the controlling device, wherein said second controller outputs the throttle rate in the form of a pulse signal whose duty cycle varies in accordance with the detected one of the present CPU load and the remaining battery capacity, and wherein the controlling device includes a throttle controller providing the data bus with the throttled clock only when the pulse signal is in a specific state.  
 
     
     
       26. A bus clock controlling method in a computer, comprising:
   setting a throttle rate of a first clock to a predetermined initial value, the first clock being for a data bus to which both a CPU and a controlling device are connected;        detecting a load of the CPU; and        adjusting the set throttle rate according to the detected CPU load,        wherein a second clock is provided to the controlling device and the CPU,        the throttle rate of the first clock is set independently of the second clock, and        the first clock has a different value than the second clock.      
     
     
       27. The method of  claim 26 , wherein a third clock is provided to the CPU, and the first clock has a different value than the third clock.  
     
     
       28. The method of  claim 26 , wherein in the adjusting step, the throttle rate of the first clock is increased when the load of the CPU is decreased, and/or the throttle rate of the first clock is decreased when the load of the CPU is increased.  
     
     
       29. A method for controlling a bus clock frequency in a computer, the computer including a CPU, a controlling device, and a host data bus connected between the CPU and the controlling device, the method comprising:
   providing a predetermined clock to the CPU through the host data bus connected between the CPU and the controlling device;        determining a current load of the CPU; and        changing, by the controlling device, a throttle rate of the clock applied to the CPU to a predetermined value based on the determined load of the CPU, wherein the throttle rate is changed when the controlling device is providing the clock to the data bus between the CPU and the controlling device.      
     
     
       30. The method of  claim 29 , wherein in the changing step, the throttle rate of the clock is increased when the load of the CPU is decreased, and/or the throttle rate of the clock is decreased when the load of the CPU is increased.  
     
     
       31. The method of  claim 29 , further comprising:
   applying another clock signal to each of the CPU and the controlling device.      
     
     
       32. A computer, comprising:
   a CPU, a controlling device, and a data bus coupled between the CPU and the controlling device,        wherein the CPU, the controlling device and the data bus are operatively coupled and the computer is configured to:        set a throttle rate of a first clock to a predetermined initial value, the first clock being for the data bus;        detect a load of the CPU; and        adjust the set throttle rate according to the detected CPU load,        wherein a second clock is provided to the controlling device and the CPU,        the throttle rate of the first clock is set independently of the second clock, and        the first clock has a different value than the second clock.      
     
     
       33. The computer of  claim 32 , further comprising:
   a clock generator configured to generate a third clock to the CPU, the first clock having a different value than the third clock.      
     
     
       34. The computer of  claim 32 , wherein the throttle rate of the first clock is increased when the load of the CPU is decreased, and/or the throttle rate of the first clock is decreased when the load of the CPU is increased.  
     
     
       35. A computer, comprising:
   a CPU, a controlling device, and a host data bus connected between the CPU and the controlling device,        wherein the CPU, the controlling device and the data bus are operatively coupled and the computer is configured to:        provide a predetermined clock to the CPU through the host data bus connected between the CPU and the controlling device;        determine a current load of the CPU; and        change, by the controlling device, a throttle rate of the clock applied to the CPU to a predetermined value based on the determined load of the CPU, wherein the throttle rate is changed when the controlling device is providing the clock to the data bus between the CPU and the controlling device.      
     
     
       36. The computer of  claim 35 , wherein the throttle rate of the clock is increased when the load of the CPU is decreased, and/or the throttle rate of the clock is decreased when the load of the CPU is increased.  
     
     
       37. The computer of  claim 35 , further comprising:
   a clock generator configured to apply another clock signal to each of the CPU and the controlling device.      
     
     
       38. The method of  claim 1 , wherein the step of adjusting the set throttle rate of the clock includes changing a duty cycle of the clock in reverse relation to the detected remaining battery capacity.  
     
     
       39. The method of  6 , wherein the step of adjusting the set throttle rate of the clock includes changing a duty cycle of the clock in reverse relation to the detected present load of the CPU.  
     
     
       40. The computer of  claim 10 , wherein the second controller adjusts the throttle rate of the clock by adjusting a duty cycle of the clock in reverse relation to the remaining battery capacity or the load of the CPU.  
     
     
       41. The method of  claim 18 , wherein the step of adjusting the set throttle rate of the clock includes changing a duty cycle of the clock in reverse relation to the detected remaining battery capacity or the detected CPU load.  
     
     
       42. The method of  claim 20 , wherein the step of adjusting the set throttle rate of the clock includes changing a duty cycle of the clock in reverse relation to the remaining battery capacity or the CPU load.  
     
     
       43. The method of  claim 24 , wherein the step of adjusting the set throttle rate of the clock includes changing a duty cycle of the clock in reverse relation to the detected one of the present CPU load and the remaining battery capacity.  
     
     
       44. The method of  claim 26 , wherein the step of adjusting the set throttle rate of the first clock includes changing a duty cycle of the first clock in reverse relation to the detected CPU load.  
     
     
       45. The method of  claim 29 , wherein the step of changing the throttle rate of the clock includes changing a duty cycle of the clock in reverse relation to the determined load of the CPU.  
     
     
       46. The computer of  claim 32 , wherein the computer adjusts the set throttle rate of the first clock by adjusting a duty cycle of the first clock in reverse relation to the detected load of the CPU.  
     
     
       47. The computer of  claim 35 , wherein the computer adjusts the throttle rate of the clock by adjusting a duty cycle of the clock in reverse relation to the determined current load of the CPU.