CMOS image sensor having a chopper-type comparator to perform analog correlated double sampling

Abstract

A CMOS image sensor performing an analog correlated double sampling is disclosed. The CMOS image sensor may include an image capture device for capturing an image for analog image signal from an object an analog-to-digital converter for converting the analog image signal to a digital value using a ramp signal. In such an arrangement the analog-to-digital converter may includes a chopper-type comparator receiving the analog image signal and the ramp signal and a capacitor for receiving a start voltage of the ramp signal and charging a voltage level corresponding the start voltage of the ramp signal in a reset mode and for receiving a down-ramping signal of the ramp signal in a count mode in order to remove an device offset voltage. The analog-to-digital converter may also include a ramp signal generator providing the ramp signal to the analog-to-digital converter.

1. A CMOS image sensor comprising:
 an image capturer for capturing an image and producing an analog image signal from an object;  
 an analog-to-digital converter for converting the analog image signal to a digital value using a ramp signal, wherein the analog-to-digital converter includes: 
 a) a chopper-type comparator receiving the analog image signal and the ramp signal; and  
 b) a capacitor for receiving a start voltage of the ramp signal and charging a voltage level corresponding the start voltage of the ramp signal in a reset mode and for receiving a down-ramping signal of the ramp signal in a count mode in order to remove a device offset voltage; and  
 
 a ramp signal generator providing the ramp signal to the analog-to-digital converter.  
 
     
     
       2. The CMOS image sensor as recited in  claim 1 , further comprising a latch circuit for storing the digital value converted by the analog-to-digital converter, wherein the latch circuit has a plurality of buffer lines to store the digital value only, wherein the capacitor is a first capacitor and wherein the chopper- type comparator comprises: a plurality of capacitors and switches; and at least two inverting amplifiers, wherein the switches are controlled by a digital controller in the CMOS image sensor . 
     
     
       3. The CMOS image sensor as recited in  claim 1 , wherein the capacitor is a first capacitor and wherein the chopper-type comparator comprises:
 a plurality of capacitors and switches; and  
 at least two inverting amplifiers, wherein the switches are controlled by a digital controller in the CMOS image sensor.  
 
     
     
       4. The CMOS image sensor as recited in  claim 3 , wherein the chopper-type comparator comprises:
 a first switch connected to the image capturer;  
 a second switch connected to the ramp signal generator;  
 a second capacitor connected to the first switch, wherein the first capacitor is connected between the first switch and the second switch;  
 a first inverting amplifier connected to the second capacitor;  
 a third switch connected between input and output terminals of the first inverting amplifier;  
 a third capacitor connected to the first inverting amplifier;  
 a fourth switch connected between input and output terminals of the  a second inverting amplifier; and  
 awherein the second inverting amplifier is connected to the third capacitor and the latch circuit to store the digital value.  
 
     
     
       5. The CMOS image sensor as recited in  claim 4 , wherein the first switch is turned on in response to a control signal from the digital controller in the rest  reset mode and in a charge transfer mode in which photocharges are transferred to the analog-to-digital converter. 
     
     
       6. The CMOS image sensor as recited in  claim 5 , wherein the first, third, and fourth switches are turned on in response to a control signal from the digital controller in the charge transfer mode in which photocharges are transferred to the analog-to-digital converter. 
     
     
       7. A method for removing a device offset voltage in a CMOS image sensor, the method comprising:
 charging a start voltage of a ramp signal in a capacitor and simultaneously charging a rest  reset voltage of an image capturer in a chopper-type comparator in a reset mode;  
 providing to the chopper-type comparator an analog image signal from the image capturer in a charge transfer mode; and  
 providing a down-ramping signal of the ramp signal to the chopper-type comparator in a count mode.  
 
     
     
       8. A CMOS image sensor comprising:
   an image capturer including a plurality of pixel sensor circuits configured to provide analog signals in a reset mode and a read mode, wherein each pixel sensor circuit is further configured to provide a reset signal in the reset mode and a pixel output signal in the read mode, and wherein an offset signal is superimposed on the reset signal and the pixel output signal of each pixel sensor circuit;        a ramp signal generator configured to provide a ramp signal, wherein the ramp signal includes a ramp signal waveform beginning as a start signal;        a chopper circuit configured to receive the analog signals and the ramp signal, wherein the chopper circuit is further configured to generate a control signal to control operation of a logic component, and wherein the chopper circuit is further configured such that:        during the reset mode, the chopper circuit generates a reset mode signal corresponding to a difference between first and second signals, wherein the first signal includes the reset signal, wherein the second signal includes a sum of the offset signal and the start signal, and wherein the reset signal, offset signal, and start signal are sampled concurrently;        during the read mode, the chopper circuit generates a clamped logic level signal, wherein the chopper circuit further generates a read mode signal that corresponds to a difference between the pixel output signal and a third signal, and wherein the third signal includes a sum of the offset signal and the clamped logic level signal; and        during the read mode, the chopper circuit generates the control signal using a signal corresponding to a difference between the reset mode signal and the read mode signal.     
     
     
       9. The CMOS image sensor of  claim 8 , wherein the ramp signal waveform includes a down- ramping waveform.   
     
     
       10. The CMOS image sensor of  claim 8 , wherein the chopper circuit comprises:
   a plurality of capacitors and switches; and        at least two inverting amplifiers, wherein the switches are configured to respond to control signals provided by a digital controller in the CMOS image sensor.     
     
     
       11. The CMOS image sensor of  claim 10 , wherein the chopper circuit further comprises:
   a first switch configured to receive the analog signals from the image capturer;        a second switch configured to receive the ramp signal from the ramp signal generator;        a first capacitor connected between the first switch and the second switch;        a first inverting amplifier connected to the first capacitor;        a third switch connected between input and output terminals of the first inverting amplifier;        a second capacitor connected between the first switch and the input terminal of the first inverting amplifier;        a second inverting amplifier;        a third capacitor connected between the output terminal of the first inverting amplifier and an input terminal of the second inverting amplifier;        a fourth switch connected between input and output terminals of the second inverting amplifier;        wherein the output terminal of the second inverting amplifier is provided as the control signal from the chopper circuit.     
     
     
       12. The CMOS image sensor of  claim 11 , wherein the first, second, third, and fourth switches are configured to respond to control signals from the digital controller. 
     
     
       13. The CMOS image sensor of  claim 8 , further comprising a latch circuit configured to store a digital value of a digital counter if a difference between the reset mode signal and the read mode signal corresponds to a magnitude of the ramp signal waveform. 
     
     
       14. A method of compensating for an offset voltage of a pixel sensor in a CMOS image sensor, the method comprising:
   providing a reset voltage from the pixel sensor during a reset mode, wherein the offset voltage is superimposed on the reset voltage;        providing a ramp voltage waveform beginning at a start voltage;        concurrently sampling the reset voltage, the offset voltage superimposed on the reset voltage, and the start voltage;        generating a reset mode voltage, wherein the reset mode voltage corresponds to a difference between first and second voltages, wherein the first voltage includes the reset voltage, and wherein the second voltage includes a sum of the offset voltage and the start voltage;        generating a clamped logic level voltage;        providing a pixel output voltage during a pixel sensor read mode, wherein the offset voltage is superimposed on the pixel output voltage;        generating a read mode voltage corresponding to a difference between the pixel output voltage and a third voltage, wherein the third voltage includes a sum of the offset voltage and the clamped logic level voltage; and        generating a control signal to a logic circuit, wherein the control signal corresponds to a difference between the reset mode voltage and the read mode voltage.     
     
     
       15. The method of  claim 14 , wherein said generating a reset mode voltage comprises:
   configuring a capacitor to receive the reset voltage and the offset voltage at a first terminal; and        configuring the capacitor to receive the start signal at a second terminal.     
     
     
       16. A CMOS image sensor comprising: an image capturer including a plurality of pixel sensor circuits, wherein each pixel sensor circuit is configured to provide a reset signal in a reset mode and a pixel output signal in a read mode, and wherein an offset signal is superimposed on the reset signal and the pixel output signal of each pixel sensor circuit during the reset mode and read mode, respectively;
   a ramp signal generator configured to provide a ramp signal, wherein the ramp signal includes a ramp signal waveform beginning as a start signal;        a chopper circuit configured to receive the reset signal with the superimposed offset signal from a given pixel sensor circuit during the reset mode and the pixel output signal with the superimposed offset signal from the given pixel sensor circuit during the read mode, wherein the chopper circuit is configured to receive the ramp signal from the ramp signal generator, and wherein the chopper circuit is configured to generate a control signal to control operation of a logic component;        wherein, during the reset mode, the chopper circuit is configured to generate a reset mode signal across a charging element by concurrently sampling the reset signal and the offset signal from the given pixel sensor circuit and the start signal from the ramp signal generator, wherein the reset mode signal corresponds to a difference between first and second signals, and wherein the first signal includes the reset signal, and wherein the second signal includes a sum of the offset signal and the start signal;        wherein, during the read mode, the chopper circuit is further configured to generate a clamped logic level signal and is further configured to generate a read mode signal that corresponds to a difference between the pixel output signal and a third signal, wherein the third signal includes a sum of the offset signal and the clamped logic level signal; and        wherein, during the read mode, the chopper circuit is further configured to generate the control signal using a signal corresponding to a difference between the reset mode signal and the read mode signal.     
     
     
       17. The CMOS image sensor of  claim 16 , wherein the charging element comprises a capacitor connected between first and second inputs of the chopper circuit. 
     
     
       18. A CMOS image sensor comprising:
   an image capturer having a plurality of pixel sensor circuits, wherein each pixel sensor circuit is configured to provide an analog signal at its output;        a ramp signal generator configured to provide a ramp signal;        a chopper circuit configured to receive the analog signal from a given pixel sensor circuit and to receive the ramp signal from the ramp signal generator, wherein the chopper circuit is configured to:      provide a logic level control signal to control operation of a logic component, wherein the logic level control signal is used to generate a digital signal corresponding to a magnitude of the analog signal provided from the output of the given pixel sensor circuit; and        store a signal across a charging element, wherein the signal stored across the charging element corresponds to a difference between the analog signal from the given pixel sensor circuit and the ramp signal from the ramp signal generator, wherein the analog signal from the given pixel sensor circuit and the ramp signal from the ramp signal generator are concurrently sampled to store the signal across the charging element during a mode of at least two modes of operation of the given pixel sensor circuit to generate the logic level control signal to the logic component, wherein the charging element comprises a capacitor connected between first and second inputs of the chopper circuit.       
     
     
       19. The CMOS image sensor of  claim 18 , wherein the at least two modes of operation comprise a reset mode in which a reset signal is provided from the output of the given pixel sensor circuit and a read mode in which a pixel output signal is provided from the output of the given pixel sensor circuit.