Methods and apparatus for providing direct memory access control

Abstract

Techniques are described for providing mechanisms of data distribution to and collection of data from multiple memories in a data processing system. The system may suitably be a manifold array (ManArray) processing system employing an array of processing elements. Virtual to physical processing element (PE) identifier translation is employed in conjunction with a ManArray PE interconnection topology to support a variety of communication models, such as hypercube and such. Also, PE addressing nodes are based upon logically nested parameterized loops. Mechanisms for updating loop parameters, as well as exemplary instruction formats are also described.

1. An apparatus for performing virtual identification (VID) to physical identification (PID) translation for data elements to be accessed within local memory of a processing element (PE) whereby a direct memory access (DMA) controller can access PE local memories according to their VIDs, the apparatus comprising:
 an array of multiple PEs each having local PE memory;    a DMA controller; and    a memory maintained in the DMA controller for storing a processing element VID-to-PID table mapping processing element VIDs to processing element PIDs utilized by the DMA controller to access local memories according to their VIDs.    
     
     
       2. The apparatus of  claim 1  wherein said memory is maintained in a core transfer unit of the DMA controller. 
     
     
       3. The apparatus of  claim 2  wherein the core transfer unit (CTU) further comprises an address generation unit (AGU) which receives a CTU transfer instruction which specifies a starting address which is used by the AGU to generate an initial VID. 
     
     
       4. The apparatus of  claim 3  wherein the initial VID controls the selection of one of the elements of the VID-to-PID lookup table through a multiplexer. 
     
     
       5. The apparatus of  claim 4  further comprising a DMA bus for providing the selected PID as a first component of a PE address. 
     
     
       6. The apparatus of  claim 5  wherein the AGU further operates to generate a PE memory offset which is sent as a second component of a PE address on the DMA bus. 
     
     
       7. The apparatus of  claim 6  further comprising a local memory interface unit (LMIU) which is used to compare the PID sent on the DMA bus to a stored PID for any DMA access, if a match is detected then the LMIU accepts the access. 
     
     
       8. The apparatus of  claim 3  wherein successive VIDs are generated in recursive fashion by the AGU. 
     
     
       9. The apparatus of  claim 3  wherein successive VIDs are generated in recursive fashion by the AGU, and further comprising:
 a local memory interface unit for each processing element (PE) storing a VID for each PE.    
     
     
       10. The apparatus of  claim 9  wherein a VID available to a particular LMIU or a DMA bus is compared with the stored VID in the LMIU and where a match occurs the LMIU accepts the access. 
     
     
       11. The apparatus of  claim 1  wherein the VID-to-PID table is stored in a programmable register and the programmable register is loaded utilizing a DMA instruction. 
     
     
       12. The apparatus of  claim 1  wherein the VID-to-PID table is stored in a programmable register and the programmable register loaded utilizing a direct write to the programmable register. 
     
     
       13. A processing apparatus comprising:
 a plurality of processing elements (PEs) communicatively connected by a bus, each PE comprising a register storing a virtual identification number (VID) identifying the PE; and    a direct memory access (DMA) controller connected to the bus for accessing local data memory of the PEs, each data access at least partially identified by a VID;    wherein during a common data to access multiple PEs, a PE responds to the data access if the VID stored in the register matches the VID of the data access.    
     
     
       14. The processing apparatus of  claim 13  wherein each PE comprises a local memory interface unit (LMIU) which includes the register storing the VID. 
     
     
       15. The processing apparatus of  claim 13  wherein the data access is a read access. 
     
     
       16. The processing apparatus of  claim 13  wherein the data access is a write access. 
     
     
       17. The processing apparatus of  claim 13  further comprising: means for updating the register. 
     
     
       18. An apparatus for accessing local memory of a plurality of processing elements ( PEs ) , the apparatus comprising:      a transfer controller running a process containing a set of nested loops, the set of nested loops having a plurality of parameters to be specified by a transfer instruction, the plurality of parameters, when assigned, control PE selection and address generation for accessing a memory location in local memory of each selected PE; and        a means for receiving the transfer instruction for transferring data between system memory and local memory of the plurality of PEs, the transfer instruction having fields which specify values for the plurality of parameters, the transfer instruction indicating an addressing mode, the addressing mode specifying a particular pattern of accessing local memory of the plurality of PEs, wherein the transfer controller decodes the transfer instruction to assign values to the plurality of parameters, the process generating addresses for accessing a memory location in local memory of each selected PE in a particular pattern, wherein the particular pattern is based on the assigned parameters.     
     
     
       19. The apparatus of  claim 18  wherein the means for receiving a transfer instruction is an instruction control unit. 
     
     
       20. The apparatus of  claim 18  wherein the means for receiving a transfer instruction is a core transfer unit reading instructions from a memory attached to a direct memory access ( DMA )  bus.   
     
     
       21. The apparatus of  claim 18  wherein the means for receiving a transfer instruction is a system data bus connected to the transfer controller and system memory. 
     
     
       22. The apparatus of  claim 18  wherein the transfer instruction specifies a block cyclic addressing mode. 
     
     
       23. The apparatus of  claim 18  wherein the transfer instruction specifies a PE select index addressing mode. 
     
     
       24. The apparatus of  claim 18  wherein the transfer instruction specifies a select PE addressing mode. 
     
     
       25. The apparatus of  claim 18  wherein the transfer instruction specifies a select index PE mode. 
     
     
       26. A method of accessing local memory of a plurality of processing elements ( PEs ) , the method comprising:      receiving a transfer instruction for transferring data between system memory and the local memory of a plurality of processing elements  ( PEs );      running a process containing a set of nested loops, the set of nested loops having a plurality of parameters to be assigned values of fields carried in the transfer instruction;        decoding the transfer instruction to assign field values to the plurality of parameters;        assigning the field values to the plurality of parameters in order to control PE selection and address generation for accessing a memory location in local memory of each selected PE; and        generating addresses to access local memory of each PE in a defined pattern.     
     
     
       27. The method of  claim 26  wherein the transfer instruction specifies a block cyclic addressing mode. 
     
     
       28. The method of  claim 26  wherein the transfer instruction specifies a PE select index addressing mode. 
     
     
       29. The method of  claim 26  wherein the transfer instruction specifies a select PE addressing mode. 
     
     
       30. The method of  claim 26  wherein the transfer instruction specifies a select index PE mode.