Power conversion integrated circuit and method for programming

Abstract

A single input pin ( 48 ) provides multi-functional features for programming a power supply ( 10 ). By connecting the appropriate interface circuit ( 92, 100, or 112 ) to the single input pin ( 48 ), the power supply ( 10 ) is programmed for specific behaviors during power up and toggling of an on/off switch ( 96, 108 ). In one mode of operation a light emitting diode ( 106 ) in the interface circuit ( 100 ) is optically coupled to a microprocessor for signaling the closure of the on/off switch ( 108 ), allowing the microprocessor to control the power supply ( 10 ) through an opto-coupler ( 102 ). In another mode of operation, the single on/off switch ( 96 ) controls the power supply ( 10 ). In yet another mode of operation, Zener diode ( 118 ) in the interface circuit ( 112 ) controls the power supply ( 10 ) during brown-out and black-out conditions.

1. A power conversion integrated circuit, comprising:
 a state circuit having an output that supplies a mode signal, wherein the state circuit includes 
 a comparator having a first input coupled for receiving a control signal and a second input coupled for receiving a first reference signal, and  
 a memory circuit having a first input coupled to an output of the comparator for setting an output state of the memory circuit according to a value of the control signal; and  
   a control circuit coupled for receiving the mode signal that sets a mode of operation, where the control circuit is responsive to a feedback signal for providing a pulse-width modulated control signal.    
     
     
       2. The power conversion integrated circuit of  claim 1 , wherein the comparator includes:
 a first comparator having a first input coupled for receiving the control signal, a second input coupled for receiving the first reference signal, and an output coupled to the first input of the memory circuit; and    a second comparator having a first input coupled for receiving the control signal, a second input coupled for receiving a second reference signal, and an output coupled to a second input of the memory circuit.    
     
     
       3. The power conversion integrated circuit of  claim 2 , further including a resistor divider network for generating the first reference signal at a first output and the second reference signal at a second output. 
     
     
       4. The power conversion integrated circuit of  claim 3 , wherein the resistor divider network includes:
 a first resistor having first and second terminals, the first terminal of the first resistor coupled to a first power supply conductor;    a second resistor having first and second terminals, the first terminal of the second resistor coupled to the second terminal of the first resistor and serving as the first output of the resistor divider network; and    a third resistor having first and second terminals, the first terminal of the third resistor coupled to the second terminal of the second resistor and serving as the second output of the resistor divider network, and the second terminal of the third resistor coupled to a second power supply conductor.    
     
     
       5. The power conversion integrated circuit of  claim 4 , further including a pulse filter having an input coupled to the output of the second comparator and an output coupled to the second input of the memory circuit. 
     
     
       6. The power conversion integrated circuit of  claim 1 , wherein the memory circuit has at least one storage element for storing an operating mode of the power conversion integrated circuit. 
     
     
       7. The power conversion integrated circuit of  claim 1 , further including a reset circuit having an input coupled to a logic under voltage signal and an output coupled to the control signal. 
     
     
       8. A semiconductor chip having at least four external electrical connections, comprising:
 an internal regulator; a state circuit having an output coupled to a control input of the internal regulator;    a first electrical connection terminal for coupling an external ground reference to an internal ground reference of the internal regulator;    a second electrical connection terminal for providing a pulse-width modulated output signal from an output of the internal regulator;    a third electrical connection terminal coupled for receiving a feedback signal at an input of the internal regulator to control the pulse-width modulated output signal; and    a fourth electrical connection terminal coupled for receiving a control signal which is applied to the state circuit to set a mode of operation of the internal regulator.    
     
     
       9. The semiconductor chip of  claim 8 , further comprising a fifth electrical connection terminal coupled for receiving a bias voltage which is applied to the state circuit and to the internal regulator. 
     
     
       10. A programmable power supply, comprising:
 a transformer receiving a rectified signal at a primary side of the transformer;    a state circuit having an input and an output for setting a mode of operation of the programmable power supply, wherein the state circuit includes, 
 a comparator circuit having a first input coupled to the input of the state circuit for receiving a control signal and a second input coupled for receiving a first reference signal, and  
 a memory circuit having a first input coupled to an output of the comparator for setting an output state of the memory circuit according to a value of the control signal where the output state of the memory circuit controls the mode of operation;  
   a control circuit coupled for receiving the output state of the memory circuit and wherein the control circuit is responsive to a feedback signal for providing a pulse-width modulated control signal; and    a transistor having a control terminal for receiving the pulse-width modulated control signal, a first conduction terminal coupled to the primary side of the transformer, and a second conduction terminal coupled to ground.    
     
     
       11. The programmable power supply of  claim 10 , wherein the comparator circuit includes:
 a first comparator having a first input coupled for receiving the control signal, a second input coupled for receiving the first reference signal, and an output coupled to the first input of the memory circuit; and    a second comparator having a first input coupled for receiving the control signal, a second input coupled for receiving a second reference signal, and an output coupled to a second input of the memory circuit.    
     
     
       12. The programmable power supply of  claim 10 , further including a resistor divider network for generating a first reference signal at a first output and a second reference signal at a second output. 
     
     
       13. The programmable power supply of  claim 12 , wherein the resistor divider network includes:
 a first resistor having first and second terminals, the first terminal of the first resistor coupled to a first power supply conductor;    a second resistor having first and second terminals, the first terminal of the second resistor coupled to the second terminal of the first resistor and serving as the first output of the resistor divider network; and    a third resistor having first and second terminals, the first terminal of the third resistor coupled to the second terminal of the second resistor and serving as the second output of the resistor divider network, and the second terminal of the third resistor coupled to a second power supply conductor.    
     
     
       14. A method for controlling a mode of operation of a power converter, comprising the steps of:
 controlling a pulse-width modulated output signal of the power converter in response to a feedback signal; and    setting a memory state according to a comparison between a control signal and a first reference signal where the memory state controls the mode of operation of the power converter.    
     
     
       15. The method of  claim 14 , further comprising the steps of:
 monitoring a signal at an input pin; and    maintaining a same operating state when the input pin receives a voltage about midway between an operating potential and a ground reference.    
     
     
       16. The method of  claim 14 , further comprising the steps of requesting an on-operating state when a power supply is off and an input pin receives a voltage greater than a first reference voltage. 
     
     
       17. The method of  claim 14 , further comprising the steps of requesting a toggle condition when a power supply is on and an input pin receives a voltage greater than a first reference voltage. 
     
     
       18. The method of  claim 15 , further comprising the steps of requesting that an output state be toggled when a power supply is on and an input pin receives a voltage less than a second reference voltage. 
     
     
       19. The method of  claim 14 , further comprising the step of operating in an off-operating state when a brown-out occurs that includes receiving a signal that is proportional to a line voltage that is less than a second reference voltage. 
     
     
       20. The method of  claim 14 , further comprising the step of operating in an off-operating state when a black-out occurs that includes receiving a signal that is proportional to a line voltage that is less than a second reference voltage. 
     
     
       21. A power supply regulator circuit, comprising:
   a terminal adapted for receiving a mode control signal having a latchable state, wherein the latchable state of the mode control signal controls an operational on - state or a non - operational off - state of the power supply regulator circuit; and        a pulse width modulated  ( PWM )  regulator circuit having a first input coupled for receiving a feedback signal, and an output for providing a PWM switching signal in response to the feedback signal, the PWM regulator circuit including,    ( a )  a first comparator having an input coupled for receiving the mode control signal, and an output having first or second states depending on a comparison between the mode control signal and a first reference value,      ( b )  a second comparator having an input coupled for receiving the mode control signal, and an output having first or second states depending on a comparison between the mode control signal and a second reference value different from the first reference value, and      ( c )  a logic circuit having a first input coupled to the output of the first comparator, a second input coupled to the output of the second comparator, the logic circuit decoding the outputs of the first and second comparators and setting the PWM regulator circuit to the non - operational off - state to conserve energy for an extended period of time as determined by the latchable state of the mode control signal, wherein the regulator circuit is provided in a monolithic integrated circuit package and the terminal is coupled to a pin of the monolithic integrated circuit package.        
     
     
       22. The power supply regulator circuit of  claim 21 , further including a latching circuit having an output coupled to the terminal for providing the mode control signal.  
     
     
       23. The power supply regulator circuit of  claim 21 , further including a microprocessor having an output coupled to the terminal for providing the mode control signal.  
     
     
       24. The power supply regulator circuit of  claim 21 , further including a detector circuit monitoring a condition of the power supply regulator circuit and having an output coupled to the terminal for providing the mode control signal.  
     
     
       25. The power supply regulator circuit of  claim 26 , wherein the first state of the mode control signal holds the non- operational off - state of the regulator circuit to conserve energy for a period of time as determined by the mode control signal.    
     
     
       26. A power supply regulator circuit, comprising:
   a terminal coupled for receiving a mode control signal which controls on - state and off - state of the power supply regulator circuit; and        a regulator circuit having a first input coupled for receiving a feedback signal, and an output for providing a pulse - width modulated switching signal in response to the feedback signal, the regulator circuit including,    ( a )  a first comparator having an input coupled for receiving the mode control signal, and an output having first or second states depending on a comparison between the mode control signal and a first reference value,      ( b )  a second comparator having an input coupled for receiving the mode control signal, and an output having first or second states depending on a comparison between the mode control signal and a second reference value different from the first reference value, and      ( c )  a logic circuit having a first input coupled to the output of the first comparator, a second input coupled to the output of the second comparator, the logic circuit decoding the outputs of the first and second comparators and setting the regulator circuit to a non - operational off - state, wherein the regulator circuit is provided in a monolithic integrated circuit package and the terminal is coupled to a pin of the monolithic integrated circuit package.        
     
     
       27. The power supply regulator circuit of  claim 26 , further including a latching circuit having an output coupled to the terminal for providing the mode control signal.  
     
     
       28. A power supply regulator circuit, comprising:
   a terminal adapted for receiving a mode control signal which controls an on - state and off - state of the power supply regulator circuit;      a first comparator having an input coupled to the terminal for receiving the mode control signal, and an output having first or second states depending on a comparison between the mode control signal and a first reference value;        a second comparator having an input coupled for receiving the mode control signal, and an output having first or second states depending on a comparison between the mode control signal and a second reference value different from the first reference value;        a logic circuit having a first input coupled to the output of the first comparator, and a second input coupled to the output of the second comparator; and        a control circuit having a first input coupled for    receiving a feedback signal, a second input coupled for receiving an operating potential, an output for providing a switching signal in response to the feedback signal, and a control input coupled to an output of the logic circuit for setting the power supply regulator circuit to an operational state or non - operational state.        
     
     
       29. The power supply regulator circuit of  claim 28 , wherein the mode control signal holds the non- operational state of the control circuit to conserve energy for a period of time as determined by the mode control signal.    
     
     
       30. The power supply regulator circuit of  claim 28 , wherein the mode control signal has first, second, and third values.  
     
     
       31. The power supply regulator circuit of  claim 28 , wherein the control circuit remains in the non- operational off - state while the mode control signal has a first state.    
     
     
       32. The power supply regulator circuit of  claim 28 , further including a latching circuit having an output coupled to the terminal for providing the mode control signal.  
     
     
       33. The power supply regulator circuit of  claim 28 , wherein the regulator circuit is provided in a monolithic integrated circuit package.  
     
     
       34. A power supply regulator circuit, comprising:
   a multi - function terminal coupled for receiving a mode control signal which controls a plurality of operational modes of the power supply regulator circuit;        a regulator circuit having a first input coupled for receiving a feedback signal, a second input coupled for receiving an operating potential, and an output for providing a switching signal in response to the feedback signal; and        a chip disable circuit having an input coupled for receiving the mode control signal, the chip disable circuit including,    ( a )  a first comparator having an input coupled for receiving the mode control signal, and an output having first or second states depending on a comparison between the mode control signal and a first reference value,      ( b )  a second comparator having an input coupled for receiving the mode control signal, and an output having first or second states depending on a comparison between the mode control signal and a second reference value different from the first reference value, and      ( c )  a logic circuit having a first input coupled to the output of the first comparator, a second input coupled to the output of the second comparator, and an output coupled to a control input of the regulator circuit, wherein the logic circuit decodes output states of the first and second comparators to select an operational mode of the regulator circuit.        
     
     
       35. The power supply regulator circuit of  claim 34 , wherein the regulator circuit is provided in a monolithic integrated circuit package.  
     
     
       36. The power supply regulator circuit of  claim 34 , wherein the mode control signal has first, second, and third values.  
     
     
       37. The power supply regulator circuit of  claim 34 , wherein one of the plurality of operational modes is a non- operational state.    
     
     
       38. The power supply regulator circuit of  claim 37 , wherein the mode control signal holds the non- operational state of the control circuit to conserve energy for a period of time as determined by the mode control signal.    
     
     
       39. The power supply regulator circuit of  claim 37 , wherein the control circuit remains in the non- operational off - state while the mode control signal has a first state.    
     
     
       40. The power supply regulator circuit of  claim 34 , further including a latching circuit having an output coupled to the terminal for providing the mode control signal.  
     
     
       41. A power supply regulator circuit, comprising:
   a terminal adapted for receiving an external disable control signal;      a pulse width modulated  ( PWM )  regulator circuit having a first input coupled for receiving a feedback signal, a second input coupled for receiving an operating potential, and an output for providing a switching signal in response to the feedback signal; and        a chip disable circuit having an input coupled for receiving the external disable control signal for disabling operation of the PWM control circuit in response to the external disable control signal, the chip disable circuit including,      ( a )  a first comparator having an input coupled for receiving the external disable control signal, and an output having first or second states depending on a comparison between the external disable control signal and a first reference value,      ( b )  a second comparator having an input coupled for receiving the external disable control signal, and an output having first or second states depending on a comparison between the external disable control signal and a second reference value different from the first reference value, and      ( c )  a logic circuit having a first input coupled to the output of the first comparator, a second input coupled to the output of the second comparator, and an output coupled to a control input of the PWM regulator circuit;          wherein the chip disable circuit sets the power supply regulator circuit to a non - operational state to conserve energy for an extended period of time as determined by the external disable control signal.      
     
     
       42. The power supply regulator circuit of  claim 41 , wherein the regulator circuit is provided in a monolithic integrated circuit package.  
     
     
       43. The power supply regulator circuit of  claim 41 , wherein the mode control signal holds the non- operational state of the control circuit to conserve energy for a period of time as determined by the mode control signal.    
     
     
       44. The power supply regulator circuit of  claim 41 , wherein the mode control signal has first, second, and third values.  
     
     
       45. The power supply regulator circuit of  claim 41 , further including a latching circuit having an output coupled to the terminal for providing the mode control signal.  
     
     
       46. A semiconductor die having at least four external connections, comprising:
   a first electrical connection terminal coupled for receiving a feedback signal;        a second electrical connection terminal for providing a switching signal;        a third electrical connection terminal coupled to an external ground reference;        a fourth electrical connection terminal coupled for receiving an external disable control signal;        a switching regulator circuit having a first input coupled to the first electrical connection terminal for receiving the feedback signal, a second input coupled for receiving an operating potential, an output coupled to the second electrical connection terminal for providing the switching signal in response to the feedback signal, and an internal ground coupled to the third electrical connection terminal; and        a chip disable circuit having an input coupled for receiving the external disable control signal for disabling operation of the switching regulator circuit in response to the external disable control signal, the chip disable circuit including,      ( a )  a first comparator having an input coupled for receiving the external disable control signal, and an output having first or second states depending on a comparison between the external disable control signal and a first reference value,      ( b )  a second comparator having an input coupled for receiving the external disable control signal, and an output having first or second states depending on a comparison between the external disable control signal and a second reference value different from the first reference value, and      ( c )  a logic circuit having a first input coupled to the output of the first comparator, a second input coupled to the output of the second comparator, and an output coupled to a control input of the switching regulator circuit to disable operation of the semiconductor chip.      
     
     
       47. The semiconductor die of  claim 46 , wherein the external disable control signal holds a non- operational state of the switching regulator circuit to conserve energy for a period of time as determined by the external disable control signal.    
     
     
       48. The semiconductor die of  claim 46 , wherein the mode control signal has first, second, and third values.  
     
     
       49. The semiconductor die of  claim 46 , further including a latching circuit having an output coupled to the terminal for providing the mode control signal.  
     
     
       50. A method of controlling an operational state of a power conversion control circuit, comprising:
   receiving an operating potential to the power conversion control circuit on a first terminal;        regulating the power conversion control circuit in response to a feedback signal;        receiving an external disable control signal on a second terminal for selecting an on - state or an off - state of the power conversion control circuit;        comparing the external disable control signal to first and second reference values; and        setting the power conversion control circuit to a plurality of operational states depending on whether the external disable control signal is greater than the first reference value, or the external disable control signal is between the first and second reference values, or the external disable control signal is less than the second reference value.      
     
     
       51. The method of  claim 50 , wherein one of the plurality of operational modes is a non- operational state.    
     
     
       52. The method of  claim 51 , wherein the mode control signal holds the non- operational state of the control circuit to conserve energy for a period of time as determined by the mode control signal.    
     
     
       53. The method of  claim 50 , wherein the mode control signal has first, second, and third value.