Semiconductor memory device

Abstract

A semiconductor memory device is constructed to include a memory cell formed by a plurality of transistors, wherein each of gate wiring layers of all of the transistors forming the memory cell is arranged to extend in one direction.

1. A semiconductor memory device comprising:
 a memory cell formed by a plurality of transistors, gate wiring layers of all of the transistors forming said memory cell being arranged to extend in one direction, wherein: of the transistors forming said memory cell, first transistors which are coupled to word lines are arranged on an outer side of second transistors which are coupled to a power supply, within the memory cell, and    the gate wiring layers of at least two of said second transistors which are coupled to the power supply are connected to each other,    a plurality of power lines, a first one of which running within the memory cell, two word lines running on both sides of the first power line,    a second power line intersecting the first power line,    and two bit line pairs running on both sides of the second power line; and    wherein a plurality of memory cells are arranged in an array, an adjacent memory cell is arranged adjacent to a certain memory cell, and a source/drain of the transistor, forming said adjacent memory cell and a bulk layer of a substrate contact are used in common by reversing a layout of said certain cell with respect to both an x-axis direction and a y-axis direction.    
     
     
       2. The semiconductor memory device as claimed in  claim 1 , wherein: of said second transistors, a source/drain of a second transistor coupled to the power supply and a substrate contact of the power supply are used in common. 
     
     
       3. The semiconductor memory device as claimed in  claim 1 , wherein: of said second transistors, a source/drain of a second transistor coupled to another power supply which is different from said power supply and a substrate contact of the other power supply are used in common. 
     
     
       4. The semiconductor memory device as claimed in  claim 3 , wherein said first transistors and said second transistors which are coupled to said power supply are made of N-channel MOS transistors, and said second transistor which is coupled to said other power supply is made of a P-channel MOS transistor. 
     
     
       5. The semiconductor memory device as claimed in  claim 1 , which further comprises:
 signal lines including word lines; and    wherein said power lines are arranged between said signal lines in a single wiring layer.    
     
     
       6. A semiconductor memory device comprising:
 a memory cell formed by a plurality of transistors,    gate wiring layers of all of the transistors forming said memory cell being arranged to extend in one direction, wherein: of the transistors forming said memory cell, first transistors which are coupled to word lines are arranged on an outer side of second transistors which are coupled to a power supply, within the memory cell,    the gate wiring layers of at least two of said second transistors which are coupled to the power supply are connected to each other,    a plurality of power lines, a first one of which running within the memory cell,    a plurality of signal lines,    two word lines running on both sides of the first power line,    a second power line intersecting the first power line,    two bit line pairs running on both sides of the second power lines;    a plurality of memory cells being arranged in an array, and    an adjacent memory cell being arranged adjacent to a certain memory cell,    said power lines and said signal lines with respect to said adjacent memory cell are used in common with said certain memory cell by reversing a layout of said certain memory cell with respect to both an x-axis direction and a y-axis direction.    
     
     
       7. The semiconductor memory device as claimed in  claim 1 , wherein said plurality of memory cells arranged in an array, said adjacent memory cell arranged adjacent to a certain memory cell, and said source/drain of the transistors forming said adjacent memory cell and said bulk layer of a substrate contact are used in common on all four adjacent sides by reversing a layout of said certain cell with respect to both an x-axis direction and a y-axis direction. 
     
     
       8. The semiconductor memory device as claimed in  claim 1 , wherein
 said plurality of memory cells arranged in an array,    said adjacent memory cell arranged adjacent to a certain memory cell, and    said power lines with respect to said adjacent memory cell are used in common with said certain memory cell by reversing a layout of said certain memory cell with respect to an x-axis direction.    
     
     
       9. The semiconductor memory device as claimed in  claim 6 , wherein: of said second transistors, a source/drain of a second transistor coupled to the power supply and a substrate contact of the power supply are used in common. 
     
     
       10. The semiconductor memory device as claimed in  claim 6 , wherein: of said second transistors, a source/drain of a second transistor coupled to another power supply which is different from said power supply and a substrate contact of the other power supply are used in common. 
     
     
       11. The semiconductor memory device as claimed in  claim 10 , wherein said first transistors and said second transistors which are coupled to said power supply are made of N-channel MOS transistors, and said second transistor which is coupled to said other power supply is made of a P-channel MOS transistor. 
     
     
       12. The semiconductor memory device as claimed in  claim 6 , wherein
 said signal lines include word lines; and    said power lines are arranged between said signal lines in a single wiring layer.    
     
     
       13. The semiconductor memory device as claimed in  claim 6 , wherein said plurality of memory cells arranged in an array, said adjacent memory cell arranged adjacent to a certain memory cell, and a source/drain of the transistor forming said adjacent memory cell and a bulk layer of a substrate contact are used in common on all four adjacent sides by reversing a layout of said certain cell with respect to both an x-axis direction and a y-axis direction. 
     
     
       14. The semiconductor memory device as claimed in  claim 6 , wherein said plurality of memory cells arranged in an array,
 said adjacent memory cell arranged adjacent to a certain memory cell, and    said power lines with respect to said adjacent memory cell are used in common with said certain memory cell by reversing a layout of said certain memory cell with respect to an x-axis direction.    
     
     
       15. A semiconductor device comprising:
   a plurality of SRAM memory cells each formed by first and second P - channel transistors and first through fourth N - channel transistors;        first and second bit lines;        a word line;        first and second power lines;        a first wiring layer forming a gate of the first P - channel transistor and a gate of the first N - channel transistor;        a second wiring layer forming a gate of the second P - channel transistor and a gate of the second N - channel transistor;        a third wiring layer forming a gate of the third N - channel transistor that is coupled to the word line; and        a fourth wiring layer forming a gate of the fourth N - channel transistor that is coupled to the word line,        said first through fourth wiring layers extending linearly and in parallel along an x - axis direction,        each of the first and second P - channel transistors having a source/drain with a first contact that couples to the first power line;        each of the first and second N - channel transistors having a source/drain with a second contact that couples to the second power line,        the third N - channel transistor having a source/drain with a third contact that couples to the first bit line,        the fourth N - channel transistor having a source/drain with a fourth contact that couples to the second bit line,        said first through fourth contacts being used in common by adjacent memory cells,        each of the first and second power lines being arranged between the first and second bit lines such that the first and second power lines and the first and second bit lines are mutually parallel,        said word line being disposed above the first through fourth wiring layers and extending in the x - axis direction,        each of the first and second power lines and the first and second bit lines being disposed above the word line and extending in a y - axis direction that is perpendicular to the x - axis direction,        the adjacent memory cells having layouts that are reversed in the x - axis direction or the y - axis direction.     
     
     
       16. A semiconductor device comprising:
   a plurality of SRAM memory cells each formed by first and second P - channel transistors and first through fourth N - channel transistors;        first and second bit lines;        a word line;        first and second power lines;        a first wiring layer forming a gate of the first P - channel transistor and a gate of the first N - channel transistor;        a second wiring layer forming a gate of the second P - channel transistor and a gate of the second N - channel transistor;        a third wiring layer forming a gate of the third N - channel transistor; and        a fourth wiring layer forming a gate of the fourth N - channel transistor,        said first through fourth wiring layers extending linearly and in parallel along an x - axis direction,        said third and fourth wiring layers being coupled to the word line,        each of the first and second P - channel transistors having a source/drain with a first contact that couples to the first power line;        each of the first and second N - channel transistors having a source/drain with a second contact that couples to the second power line,        the third N - channel transistor having a source/drain with a third contact that couples to the first bit line,        the fourth N - channel transistor having a source/drain with a fourth contact that couples to the second bit line,        said first through fourth contacts being used in common by adjacent memory cells,        each of the first and second power lines being arranged between the first and second bit lines such that the first and second power lines and the first and second bit lines are mutually parallel,        said word line being disposed above the first through fourth wiring layers and extending in the x - axis direction,        each of the first and second power lines and the first and second bit lines being disposed above the word line and extending in a y - axis direction that is perpendicular to the x - axis direction,        the adjacent memory cells having layouts that are reversed in the x - axis direction or the y - axis direction.     
     
     
       17. A semiconductor device comprising:
   a plurality of SRAM memory cells each formed by first and second P - channel transistors and first through fourth N - channel transistors;        first and second bit lines;        a word line;        first and second power lines;        a first wiring layer forming a gate of the first P - channel transistor and a gate of the first N - channel transistor;        a second wiring layer forming a gate of the second P - channel transistor and a gate of the second N - channel transistor;        a third wiring layer forming a gate of the third N - channel transistor; and        a fourth wiring layer forming a gate of the fourth N - channel transistor,        said first through fourth wiring layers extending linearly and in parallel along an x - axis direction,        said third and fourth wiring layers being extending linearly to adjacent memory cells that are adjacent to each other along the x - axis direction and being used in common by the adjacent memory cells that are adjacent to each other along the x - axis direction,        said third N - channel transistor having a source/drain which is used in common as a first bit line contact by adjacent memory cells that are adjacent to each other along a y - axis direction that is perpendicular to the x - axis direction,        said fourth N - channel transistor having a source/drain which is used in common as a second bit line contact by the adjacent memory cells that are adjacent to each other along the y - axis direction,        said third and fourth wiring layers being coupled to word line,        each of the first and second power lines being arranged between the first and second bit lines such that the first and second power lines and the first and second bit lines are mutually parallel,        said word line being disposed above the first through fourth wiring layers and extending in the x - axis direction,        each of the first and second power lines and the first and second bit lines being disposed above the word line and extending in the y - axis direction,        the adjacent memory cells having layouts that are reversed in the x - axis direction or the y - axis direction.     
     
     
       18. The semiconductor device as claimed in  claim 17 , wherein each of the first and second P- channel transistors has a source/drain with a first contact that couples to the first power line, and each of the first and second N - channel transistors has a source/drain with a second contact that couples to the second power line.   
     
     
       19. The semiconductor device as claimed in  claim 18 , wherein each of the first and second contacts is used in common by adjacent memory cells.