Circuitry to provide a low power input buffer

Abstract

Input buffer circuitry that prevents high voltage output from high voltage circuitry from being applied to connected low voltage circuitry. An input of the input buffer circuitry receives signals from the high voltage circuitry. Pinch-off circuitry receives the input signals and prevents voltage above a threshold voltage from being applied to an output of the pinch-off circuitry. Boost circuitry controls the threshold voltage of the pinch-off circuitry and pull-up circuitry draws voltage from the output of the pinch-off circuitry to regulate the control by the booster circuitry.

1. An input buffer circuitry that connects low power circuitry to high power circuitry wherein said low power circuitry operates at a first voltage and said high power circuitry operates at a second voltage that is greater than said first voltage comprising:
 an input that receives signals at said second voltage from said high power circuitry;  
 pinch-off circuitry that receives said signals and prevents voltage above a threshold voltage from being applied to an output of said pinch-off circuitry wherein said pinch-off circuitry includes a first pinch-off transistor and a second pinch-off transistor and wherein said first pinch-off transistor and said second pinch-off transistor are n-channel transistors;  
 boost circuitry that controls said threshold voltage of said pinch-off circuitry; and  
 pull-up circuitry that connects to said output of said pinch-off circuitry to draw current from said output of said pinch-off circuitry.  
 
     
     
       2. The input buffer circuitry of  claim 1  wherein said pull-up circuitry is connected to said boost circuitry to regulate control of said threshold voltage from said current drawn by said pull-up circuitry. 
     
     
       3. The input buffer circuitry of  claim 1  wherein said pinch-off circuitry comprises:  a pinch-off transistor. 
     
     
       4. The input buffer circuitry of  claim 3  wherein said pinch-off transistor is an N-channel transistor. 
     
     
       5. The input buffer circuitry of  claim 3  further comprising:
 a source of said pinch-off transistor connected to said input;  
 a drain of said pinch-off circuit  transistor connected to buffer circuitry and said pull-up circuitry; and  
 a gate of said pinch-off transistor connected to said boost circuitry.  
 
     
     
       6. The input buffer circuitry of  claim 5  wherein said boost circuitry is a pull-up transistor. 
     
     
       7. The input buffer circuitry of  claim 6  wherein said pull-up transistor is a P-channel transistor. 
     
     
       8. The input buffer circuitry of  claim 6  further comprising:
 a source of said pull-up transistor connected to a power supply;  
 a drain of said pull-up transistor connected to said gate of said pinch-off transistor; and  
 a gate of said pull-up transistor is connected to ground.  
 
     
     
       9. The input buffer circuitry of  claim 8  wherein said power supply is 3.3 volts. 
     
     
       10. The input buffer circuitry of  claim 8  wherein said pull-up circuitry comprises:  a bootstrap capacitor. 
     
     
       11. The input buffer circuitry of  claim 9  further comprising:
 an input of said bootstrap capacitor connected to said drain of said pinch-off capacitor  transistor; and  
 an output of said bootstrap capacitor connected to said drain of said pull-up transistor.  
 
     
     
       12. The input buffer circuitry of  claim 1  further comprising:
 a source of said first pinch-off transistor connected to said input;  
 a drain of said first pinch-off circuit  transistor connected to buffer circuitry and said pull-up circuitry;  
 a gate of said first pinch-off transistor connected to said boost circuitry;  
 a source of said second pinch-off transistor connected to said input;  
 a drain of said second pinch-off circuit  transistor connected to said buffer circuitry and said pull-up circuitry; and  
 a gate of said second pinch-off transistor connected to a power supply.  
 
     
     
       13. The input buffer circuitry of  claim 12  wherein said boost circuitry comprises:  a pull-up transistor. 
     
     
       14. The input buffer circuitry of  claim 12  wherein said pull-up transistor is a P-channel transistor. 
     
     
       15. The input buffer circuitry of  claim 12  further comprising:
 a source of said pull-up transistor connected to said power supply; and  
 a drain of said pull-up transistor connected to said gate of said first pinch-off transistor.  
 
     
     
       16. The input buffer circuitry of  claim 15  wherein said pull-up circuitry comprises:
 a first reverse bias diode; and  
 a second reverse bias diode.  
 
     
     
       17. The input buffer circuitry of  claim 16  wherein said first reverse bias diode comprises a first reverse bias diode transistor and said second reverse bias diode comprises a second reverse bias diode transistor. 
     
     
       18. The input buffer circuitry of  claim 17  wherein said first reverse bias diode transistor and said second reverse bias diode transistor are N-channel transistors. 
     
     
       19. The input buffer circuitry of  claim 17  further comprising:
 a source of said first reverse bias diode transistor connected to said drain of said first pinch-off transistor and said drain of said second pinch-off transistor;  
 a drain of said first reverse bias diode transistor connected to a source of said second reverse bias diode transistor;  
 a gate of said first reverse bias diode transistor connected to said drain of said first pinch-off transistor and said drain of said second pinch-off transistor;  
 a drain of said second pinch-off transistor connected to said gate and said drain of said pull-up transistor and said gate of said first pinch-off transistor; and  
 a gate of said second pinch-off transistor connected to said gate and said drain of said pull-up transistor and said gate of said first pinch-off transistor.  
 
     
     
       20. An input buffer circuit connecting a first circuit to a second circuit, wherein said first circuit operates at a first voltage and said second circuit operates at a second voltage that is greater than said first voltage, the input buffer circuit comprising:
   pinch - off circuitry configured to receive said second voltage from said second circuit and to prevent a voltage above a threshold voltage from being applied to an output of said pinch - off circuitry, wherein said pinch - off circuitry comprises both a first pinch - off transistor and a second pinch - off transistor, and wherein said first pinch - off transistor and said second pinch - off transistor are N - channel transistors; and        boost circuitry, including a transistor, configured to receive a supply voltage and to apply a source voltage to said pinch - off circuitry in response to said supply voltage, wherein said pinch - off circuitry is further configured to apply a voltage corresponding to said first voltage to said output of said pinch - off circuitry in response to said source voltage.     
     
     
       21. The input buffer circuit of  claim 20 , wherein said transistor in said boost circuitry is a P- channel transistor.   
     
     
       22. The input buffer circuit of  claim 20 , wherein:
   a source of said transistor in said boost circuitry is connected to a power supply;        a drain of said transistor in said boost circuitry is connected to a gate of a pinch - off transistor in said pinch - off circuitry; and        a gate of said transistor in said boost circuitry is connected to ground.     
     
     
       23. The input buffer circuit of  claim 20 , wherein said first pinch- off transistor comprises a source connected to an input, a drain connected to buffer circuitry and pull - up circuitry, and a gate connected to said boost circuitry, and wherein said second pinch - off transistor comprises a source connected to said input, a drain connected to said buffer circuitry and said pull - up circuitry, and a gate connected to a power supply.   
     
     
       24. The input buffer circuit of  claim 20 , further comprising pull- up circuitry connected to said output of said pinch - off circuitry and configured to draw current from said output of said pinch - off circuitry.   
     
     
       25. The input buffer circuit of  claim 24 , wherein said pull- up circuitry is further connected to said boost circuitry and configured to regulate control of said threshold voltage from said current drawn by said pull - up circuitry.   
     
     
       26. The input buffer circuit of  claim 24 , wherein said pull- up circuitry comprises at least one diode configured to draw current from said output of said pinch - off circuitry.   
     
     
       27. The input buffer circuit of  claim 24 , wherein said pull- up circuitry comprises both a first reverse - bias diode and a second reverse - bias diode to collectively draw current from said output of said pinch - off circuitry.   
     
     
       28. The input buffer circuit of  claim 27 , wherein said first reverse bias diode comprises a first reverse- bias diode transistor and said second - reverse bias diode comprises a second reverse - bias diode transistor.   
     
     
       29. The input buffer circuit of  claim 28 , wherein said first reverse- bias diode transistor and said second reverse - bias diode transistor are both N - channel transistors.   
     
     
       30. A method for providing a buffer between a first circuit operating at a first voltage and a second circuit operating at a second voltage, the method comprising:
   receiving a signal from said second circuit, wherein the signal has said second voltage;        receiving a supply voltage and then applying a source voltage to pinch - off circuitry in response to said supply voltage, wherein said pinch - off circuitry is configured to prevent a voltage above a threshold voltage from being applied from an output of said pinch - off circuitry to said first circuit; and        applying a voltage corresponding to said first voltage to said output of said pinch - off circuitry in response to the source voltage.     
     
     
       31. The method of  claim 30 , further comprising receiving the supply voltage at boost circuitry, wherein the boost circuitry includes a transistor and is configured to apply said source voltage to said pinch- off circuitry.   
     
     
       32. The method of  claim 31 , wherein said transistor comprises:
   a source connected to a power supply;        a drain connected to a gate of a pinch - off transistor in said pinch - off circuitry; and        a gate connected to ground.     
     
     
       33. The method of  claim 30 , wherein said pinch- off circuitry comprises both a first pinch - off transistor and a second pinch - off transistor, and wherein said first pinch - off transistor and said second pinch - off transistor are both N - channel transistors.   
     
     
       34. The method of  claim 33 , wherein said first pinch- off transistor comprises a source connected to an input, a drain connected to buffer circuitry and pull - up circuitry, and a gate connected to boost circuitry, and wherein said second pinch - off transistor comprises a source connected to said input, a drain connected to said buffer circuitry and said pull - up circuitry, and a gate connected to a power supply.   
     
     
       35. The method of  claim 30 , further comprising drawing current from said output of said pinch- off circuitry.   
     
     
       36. The method of  claim 35 , further comprising regulating said source voltage based, at least in part, on said current drawn from said output of said pinch- off circuitry.   
     
     
       37. The method of  claim 35 , wherein said drawing current from said output of said pinch- off circuitry is performed with at least one diode.   
     
     
       38. The method of  claim 35 , wherein said drawing current from said output of said pinch- off circuitry is performed with both a first reverse - bias diode and a second reverse - bias diode.