Methods and circuitry for built-in self-testing of content addressable memories

Abstract

Methods for built-in self-test (BIST) testing and circuitry for testing a content addressable memory (CAM) core are provided. In one example, the BIST circuit includes a search port for enabling searches of the CAM core and a maintenance port for enabling addressing of locations of the CAM core. The maintenance port includes writing logic for writing to locations of the CAM core. The BIST circuit also includes a BIST controller for coordinating BIST testing of the CAM core. The BIST controller is capable of performing a BIST search on the CAM core on every cycle through the search port and performing a BIST write at selected times to the CAM core. Thus, the BIST write is capable of being performed in a same cycle as the BIST search permitting at-speed BIST. The BIST controller, performs BIST testing in a manner that limits the number of rows in the CAM that match at any given cycle, thus allowing a low-power BIST operation. The BIST controller can also be configured to coordinate simultaneous BIST testing of two or more CAM cores.

1. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core, comprising:
 a search port for enabling searches of the CAM core;    a maintenance port for enabling addressing of locations of the CAM core, the maintenance port further including writing logic for writing to locations of the CAM core;    a BIST controller for coordinating BIST testing of the CAM core, the BIST controller being capable of performing a BIST search on the CAM core on every cycle through the search port and performing a BIST write at selected times to the CAM core, the BIST write is capable of being performed in a same cycle as the BIST search; and    a maintenance port comparator being coupled between the BIST controller and a data output of the maintenance port, the maintenance port being configured to compare an expected data generated by the BIST controller with actual data provided from the data output of the maintenance port.    
     
     
       2. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core as recited in  claim 1 , further comprising:
 a search port interface for receiving test data, tag data and control signals from the BIST controller during BIST testing, the search port interface being coupled to the search port.    
     
     
       3. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core as recited in  claim 1 , further comprising:
 a search port comparator being coupled to the search port and the BIST controller, the search port comparator being configured to,    compare search addresses generated from the search port in response to BIST search and expected addresses generated by the BIST controller and communicated to the maintenance port, and    compare expected hit and multiple hit data generated by the BIST controller with generated hit and multiple hit data output through the search port.    
     
     
       4. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core as recited in  claim 1 , further comprising:
 a BIST maintenance interface for communicating test data to the CAM core.    
     
     
       5. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core, comprising:
 a search port for enabling searches of the CAM core;    a maintenance port for enabling addressing of locations of the CAM core, the maintenance port further including writing logic for writing to locations of the CAM core; and    a BIST controller for coordinating BIST testing of the CAM core, the BIST controller being capable of performing a BIST search on the CAM core on every cycle through the search port and performing a BIST write at selected times to the CAM core, the BIST write is capable of being performed in a same cycle as the BIST search.    
     
     
       6. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core as recited in  claim 1 , wherein the search port includes multiplexer logic for selecting between BIST search data and functional search data. 
     
     
       7. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core as recited in  claim 1 , wherein the maintenance port includes multiplexer logic for selecting: (a) between BIST row and block addresses and functional mode row and block addresses; and (b) between BIST write data and functional mode write data. 
     
     
       8. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core as recited in  claim 1 , further comprising an IEEE 1149.1 controller for communicating control signals to and from the BIST controller. 
     
     
       9. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core as recited in  claim 1 , wherein BIST circuit enables BIST searches on every clock cycle, the searches performed on every cycle enabling at-speed BIST testing. 
     
     
       10. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core as recited in  claim 1 , further comprising:
 a search port comparator;    a search port interface;    a maintenance port comparator; and    a maintenance port interface;    wherein the search port interface, the maintenance port interface, the search port comparator, and the maintenance port comparator are each distributed and have expansion capabilities, which limits a number of global wires required to communicate read/write and search data and results.    
     
     
       11. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core as recited in  claim 1 , wherein the BIST testing only tests one row per cycle and the BIST testing is separate from a priority encoder (PE) BIST testing. 
     
     
       12. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core, comprising:
 a search port for enabling searches of the CAM core;    a maintenance port for enabling addressing of locations of the CAM core, the maintenance port further including writing logic for writing to locations of the CAM core;    a BIST controller for coordinating BIST testing of the CAM core, the BIST controller being capable of performing a BIST search on the CAM core on every cycle through the search port and performing a BIST write at selected times to the CAM core, the BIST write is capable of being performed in a same cycle as the BIST search; and    a search port interface that receives only 1 bit of test data from the BIST controller, other bits being generated internally to the search port interface, so as to limit a number of required global wires.    
     
     
       13. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core, comprising:
 a search port for enabling searches of the CAM core;    a maintenance port for enabling addressing of locations of the CAM core, the maintenance port further including writing logic for writing to locations of the CAM core;    a BIST controller for coordinating BIST testing of the CAM core, the BIST controller being capable of performing a BIST search on the CAM core on every cycle through the search port and performing a BIST write at selected times to the CAM core, the BIST write is capable of being performed in a same cycle as the BIST search; and    a BIST maintenance interface for communicating test data to the CAM core, the BIST maintenance interface having a capability to expand 2 bits of data from the BIST controller to a required width, the capability to expand being configured to limit a number of needed global wires.    
     
     
       14. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core, comprising:
 a search port for enabling searches of the CAM core;    a maintenance port for enabling addressing of locations of the CAM core, the maintenance port further including writing logic for writing to locations of the CAM core; and    a BIST controller for coordinating BIST testing of the CAM core, the BIST controller being capable of performing a BIST search on the CAM core on every cycle through the search port and performing a BIST write at selected times to the CAM core, the BIST write is capable of being performed in a same cycle as the BIST search, wherein BIST testing of the BIST circuit does not generate matches on all rows in the CAM core so as to enable low-power BIST operation.    
     
     
       15. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core, comprising:
 a search port for enabling searches of the CAM core;    a maintenance port for enabling addressing of locations of the CAM core, the maintenance port further including writing logic for writing to locations of the CAM core; and    a BIST controller for coordinating BIST testing of the CAM core, the BIST controller being capable of performing a BIST search on the CAM core on every cycle through the search port and performing a BIST write at selected times to the CAM core, the BIST write is capable of being performed in a same cycle as the BIST search, wherein the CAM core is a ternary CAM core that is capable of storing three states.    
     
     
       16. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core as recited in  claim 15 , wherein a word is comprised of two subrows and each of the two subrows include a plurality of binary tag bits and valid bits. 
     
     
       17. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core, comprising:
 a search port for enabling searches of the CAM core;    a maintenance port for enabling addressing of locations of the CAM core, the maintenance port further including writing logic for writing to locations of the CAM core;    a BIST controller for coordinating BIST testing of the CAM core, the BIST controller being capable of performing a BIST search and a BIST write on the CAM core at the same time, wherein the BIST search can be performed on every cycle and the BIST write can be performed at any cycle including a cycle in which the BIST search is performed.    
     
     
       18. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core as recited in  claim 17 , wherein the CAM core is a ternary CAM core that is capable of storing three states. 
     
     
       19. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core as recited in  claim 18 , wherein a word is comprised of two subrows and each of the two subrows include data bits, and binary tag bits and a valid bit, and the data bits span a 32 bit width, the binary tag bits span 2 bits and the valid bit spans 1 bit. 
     
     
       20. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core as recited in  claim 17 , further comprising:
 a search port interface for receiving test data, tag data and control signals from the BIST controller during BIST testing, the search port interface being coupled to the search port; and    a search port comparator being coupled to the search port and the BIST controller, the search port comparator being configured to,    compare search addresses generated from the search port in response to BIST search and expected addresses generated by the BIST controller and communicated to the maintenance port, and    compare expected hit and multiple hit data generated by the BIST controller with generated hit and multiple hit data output through the search port.    
     
     
       21. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core as recited in  claim 17 , further comprising:
 a BIST maintenance interface for communicating test data to the CAM core, the BIST maintenance interface having an expansion capability; and    a maintenance port comparator being coupled between the BIST controller and a data output of the maintenance port, the maintenance port being configured to compare an expected data generated by the BIST controller with actual data provided from the data output of the maintenance port.    
     
     
       22. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core as recited in  claim 17 , wherein the BIST testing only tests one row per cycle and the BIST testing is separate from a priority encoder (PE) BIST testing. 
     
     
       23. Content addressable memory (CAM) circuitry with BIST testing capabilities, comprising:
 a plurality of CAM cores;    a plurality of BIST circuits coupled to each of the CAM cores; and    a single BIST controller being capable of controlling BIST testing of each of the plurality of CAM cores.    
     
     
       24. Content addressable memory (CAM) circuitry with BIST testing capabilities as recited in  claim 23 , wherein the signal BIST controller is configured to perform BIST searches on each of the plurality of CAM cores during each cycle and is further configured to perform BIST writing during any cycle including a cycle in which the BIST search occurs. 
     
     
       25. Content addressable memory (CAM) circuitry with BIST testing capabilities as recited in  claim 24 , wherein each of the plurality of BIST circuits include:
 (a) a BIST search interface;    (b) a search port comparator;    (c) a maintenance port comparator; and    (d) a BIST maintenance interface.    
     
     
       26. A method for performing built-in self-test (BIST) testing on a content addressable memory (CAM) core, comprising:
 writing test data to memory addresses in the CAM core;    searching for test data in the CAM core, the searching being continuously performed one cycle after another and the writing of the test data capable of being performed in a same cycle as one or more search performed during the searching, wherein the CAM core is a ternary CAM core.    
     
     
       27. A method for performing built-in self-test (BIST) testing on a content addressable memory (CAM) core as recited in  claim 26 , further comprising:
 selecting one row of the CAM core to be valid during the searching, such that matches only occur in the one row in one of the cycles.    
     
     
       28. A method for performing built-in self-test (BIST) testing on a content addressable memory (CAM) core as recited in  claim 26 , wherein the CAM core has a plurality of words, and each of the plurality of words includes a plurality of binary tag bits and a valid bit. 
     
     
       29. A method for performing built-in self-test (BIST) testing on a content addressable memory (CAM) core, comprising:
 a search port for enabling searches of the CAM core;    a maintenance port for enabling addressing of locations of the CAM core, the maintenance port further including writing logic for writing to locations of the CAM core; and    a BIST controller for coordinating BIST testing of the CAM core, the BIST controller being capable of performing a BIST search and a BIST write on the CAM core at the same time.    
     
     
       30. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core, comprising:
 a maintenance port for enabling addressing of locations of the CAM core, the maintenance port further including writing logic for writing to locations of the CAM core;  
 a BIST controller for coordinating BIST testing of the CAM core, the BIST controller being capable of performing a BIST write at selected times to the CAM core, wherein the BIST controller is capable of performing a BIST search on the BIST write on the CAM core at the same time; and  
 a maintenance port comparator being coupled between the BIST controller and a data output of the maintenance port, the maintenance port comparator being configured to compare an expected data generated by the BIST controller with actual data provided from the data output of the maintanance port.  
 
     
     
       31. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core as recited in  claim 30 , further comprising:
 a BIST maintanance interface for communicating test data to the CAM core.  
 
     
     
       32. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core, comprising:
 a maintenance port for enabling addressing of locations of the CAM core, the maintanance port further including writing logic for writing to locations of the CAM core;  
 a BIST controller for coordinating BIST testing of the CAM core, the BIST controller being capable of performing a BIST write at selected times to the CAM core and performing a BIST search on the CAM core, and wherein the BIST controller is capable of performing the BIST search and the BIST write in a same cycle; and  
 a maintanance port comparator being coupled between the BIST controller and a data outpupt of the maintanance port, the maintanance port comparator being configured to compare an expected data generated by the BIST controller with actual data provided from the data output of the maintenance port.  
 
     
     
       33. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core as recited in  claim 32 , wherein the BIST search is capable of being performed on every cycle. 
     
     
       34. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core as recited in  claim 32 , further comprising:
 a search port for enabling searches the CAM core.  
 
     
     
       35. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core, comprising:
 a maintenance port for enabling addressing of locations of the CAM core, the maintenance port further including writing logic for writing to locations of the CAM core;  
 a BIST controller for coordinating BIST testing of the CAM core, the BIST controller being capable of performing a BIST write at selected times to the CAM core and performing another operation on the CAM core, the BIST write is capable of being performed in a same cycle as the another operation; and  
 a maintenance port comparator being coupled between the BIST controller and a data output of the maintanance port, the maintenance port comparator being configured to compare an expected data generated by the BIST controller with actual data provided from the data output of the maintenance port.  
 
     
     
       36. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core as recited in  claim 35 , wherein the another operation is a BIST operation. 
     
     
       37. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core as recited in  claim 35 , wherein the another operation is capable of being performed on the CAM core on every cycle. 
     
     
       38. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core as recited in  claim 35 , wherein the maintenance port includes multiplexer logic for selecting:
 (a) between BIST row and block addresses and functional mode row and block addresses; and  
 (b) between BIST write data and functional mode write data.  
 
     
     
       39. An apparatus for testing a content addressable memory (CAM) core, comprising:
   means for enabling searches of the CAM core;        means for enabling addressing of locations of the CAM core, said addressing enabling means further comprising means for writing to locations of the CAM core;        means for coordinating BIST testing of the CAM core, said BIST testing coordinating means being capable of performing a BIST search on the CAM core on every cycle through said search enabling means and performing a BIST write at selected times to the CAM core, wherein the BIST write is capable of being performed in a same cycle as the BIST search; and        maintenance port comparing means for comparing an expected data generated by said BIST testing coordinating means with actual data provided from a data output of said addressing enabling means, said maintenance port comparing means being coupled between said BIST testing coordinating means and the data output of said addressing enabling means.     
     
     
       40. The apparatus as claimed in  claim 39 , further comprising:
   means for receiving test data, tag data, or control signals, or combinations thereof, from said BIST testing coordinating means during BIST testing, said receiving means being coupled to said search enabling means.     
     
     
       41. The apparatus as claimed in  claim 39 , further comprising:
   search port comparing means for comparing search data being coupled to said search enabling means and said BIST testing coordinating means, said search port comparing means being capable of:        comparing search addresses generated from said search enabling means in response to BIST search and expected addresses generated by said BIST testing coordinating means and communicated to said addressing enabling means; and        comparing expected hit and multiple hit data generated by said BIST testing coordinating means with generated hit and multiple hit data output through said search enabling means.     
     
     
       42. The apparatus as claimed in  claim 39 , further comprising:
   means for communicating test data to the CAM core.     
     
     
       43. An apparatus for testing a content addressable memory ( CAM )  core, comprising:      means for enabling searches of the CAM core;        means for enabling addressing of locations of the CAM core, said addressing enabling means further including means for writing to locations of the CAM core; and        means for coordinating BIST testing of the CAM core, said BIST testing coordinating means being capable of performing a BIST search on the CAM core on every cycle through said search enabling means and performing a BIST write at selected times to the CAM core, wherein the BIST write is capable of being performed in a same cycle as the BIST search.     
     
     
       44. The apparatus as claimed in  claim 43 , wherein said search enabling means includes means for selecting between BIST search data and functional search data. 
     
     
       45. The apparatus as claimed in  claim 43 , wherein said addressing enabling means includes means for selecting between BIST row and block addresses and functional mode row and block addresses, or between BIST write data and functional mode write data or combinations thereof. 
     
     
       46. The apparatus as claimed in  claim 43 , further comprising means for communicating control signals to and from said BIST testing coordinating means. 
     
     
       47. The apparatus as claimed in  claim 43 , further comprising means for enabling BIST searches on one or more clock cycles, the searches being capable of being performed on one or more cycles enabling at- speed BIST testing.   
     
     
       48. The apparatus as claimed in  claim 43 , further comprising:
   search port comparing means for comparing search data;        means for receiving test data, tag data, or control signals, or combinations thereof;        maintenance port comparing means for comparing maintenance data; and        means for interfacing a means for enabling addressing of locations of the CAM core;        wherein said receiving means, said means for interfacing an addressing enabling means, said search port comparing means, or said maintenance port comparing means, or combinations thereof, are distributed and have expansion capabilities, and being capable of limiting a number of global wires required to communicate read/write or search data or results, or combinations thereof.     
     
     
       49. The apparatus as claimed in  claim 43 , wherein the BIST testing comprises testing one row per cycle and the BIST testing is separate from a priority encoder ( PE )  BIST testing.   
     
     
       50. An apparatus for testing a content addressable memory ( CAM )  core, comprising:      means for enabling searches of the CAM core;        means for enabling addressing of locations of the CAM core, said addressing enabling means further including means for writing to locations of the CAM core;        means for coordinating BIST testing of the CAM core, said BIST testing coordinating means being capable of performing a BIST search on the CAM core on every cycle through said search enabling means and performing a BIST write at selected times to the CAM core, wherein the BIST write is capable of being performed in a same cycle as the BIST search; and        means for receiving test data, tag data, or control signals, or combinations thereof capable of receiving one bit of test data from said BIST testing coordinating means, other bits being generated internally to said receiving means, and capable of limiting a number of required global wires.     
     
     
       51. An apparatus for testing a content addressable memory ( CAM )  core, comprising:      means for enabling searches of the CAM core;        means for enabling addressing of locations of the CAM core, said addressing enabling means further including means for writing to locations of the CAM core;        means for coordinating BIST testing of the CAM core, said BIST testing coordinating means being capable of performing a BIST search on the CAM core on every cycle through said search enabling means and performing a BIST write at selected times to the CAM core, the BIST write is capable of being performed in a same cycle as the BIST search; and        means for communicating test data to the CAM core, said test data communicating means having a capability to expand two bits of data from said BIST testing coordinating means to a required width, the capability to expand being capable of limiting a number of needed global wires.     
     
     
       52. An apparatus for testing a content addressable memory ( CAM )  core, comprising:      means for enabling searches of the CAM core;        means for enabling addressing of locations of the CAM core, said addressing enabling means further including means for writing to locations of the CAM core; and        means for coordinating BIST testing of the CAM core, said BIST testing coordinating means being capable of performing a BIST search on the CAM core on every cycle through said search enabling means and performing a BIST write at selected times to the CAM core, the BIST write is capable of being performed in a same cycle as the BIST search, wherein BIST testing of the BIST circuit does not generate matches on one or more rows in the CAM core so as to enable lower - power BIST operation.     
     
     
       53. An apparatus for testing a content addressable memory ( CAM )  core, comprising:      means for enabling searches of the CAM core;        means for enabling addressing of locations of the CAM core, said addressing enabling means further including means for writing to locations of the CAM core; and        means for coordinating BIST testing of the CAM core, said BIST testing coordinating means being capable of performing a BIST search on the CAM core on every cycle through said search enabling means and performing a BIST write at selected times to the CAM core, wherein the BIST write is capable of being performed in a same cycle as the BIST search wherein the CAM core is a ternary CAM core that is capable of storing three states.     
     
     
       54. The apparatus as claimed in  claim 53 , wherein a word comprises two subrows and one or more of the two subrows includes one or more binary tag bits or valid bits, or combinations thereof. 
     
     
       55. An apparatus for testing a content addressable memory ( CAM )  core, comprising:      means for enabling searches of the CAM core;        means for enabling addressing of locations of the CAM core, said addressing enabling means further including means for writing to locations of the CAM core;        means for coordinating BIST testing of the CAM core, said BIST testing coordinating means being capable of performing a BIST search and a BIST write on the CAM core at the same time, wherein the BIST search is capable of being performed on every cycle and the BIST write can be performed at any cycle including a cycle in which the BIST search is performed.     
     
     
       56. The apparatus as claimed in  claim 55 , wherein the CAM core is a ternary CAM core that is capable of storing three states. 
     
     
       57. The apparatus as claimed in  claim 56 , wherein a word comprises two subrows and each of the two subrows include data bits, or binary tag bits or a valid bit, or combinations thereof, and the data bits span a  32  bit or equivalent width, the binary tag bits span two bits or equivalent or the valid bit spans one bit or equivalent, or combinations thereof. 
     
     
       58. The apparatus as claimed in  claim 55 , further comprising:
   means for receiving test data, tag data, or control signals, or combinations thereof, from said BIST testing coordinating means during BIST testing, said receiving means being coupled to said search enabling means; and        search port comparing means for comparing search data being coupled to said search enabling means and said BIST testing coordinating means, said search port comparing means being capable of:        comparing search addresses generated from said search enabling means in response to BIST search and expected addresses generated by said BIST testing coordinating means and communicated to said addressing enabling means; and        comparing expected hit or multiple hit data, or combinations thereof, generated by said BIST testing coordinating means with generated hit or multiple hit data or combinations thereof, output through said search enabling means.     
     
     
       59. The apparatus as claimed in  claim 55 , further comprising:
   means for communicating test data to the CAM core, said test data communicating means having an expansion capability; and        maintenance port comparing means for comparing maintenance data being coupled between said BIST testing coordinating means and a data output of said addressing enabling means, said maintenance port comparing means being configured to compare an expected data generated by said BIST testing coordinating means with actual data provided from the data output of said addressing enabling means.     
     
     
       60. The apparatus as claimed in  claim 55 , wherein the BIST testing comprises testing one row per cycle and the BIST testing is separate from a priority encoder ( PE )  BIST testing.   
     
     
       61. An apparatus, comprising:
   one or more CAM cores;        means for performing a built - in self test BIST coupled to one or more of the CAM cores and capable of testing each of the one or more CAM cores; and        means for controlling said means for performing the BIST.     
     
     
       62. The apparatus as claimed in  claim 61 , wherein said controlling means is capable of performing BIST searches on one or more of the CAM cores during one or more cycles and is further capable of performing BIST writing during any cycle including a cycle in which a BIST search occurs. 
     
     
       63. The apparatus as claimed in  claim 62 , wherein the means for performing the BIST comprises:
   means for interfacing said controlling means;        search port comparing means for comparing search data;        maintenance port comparing means for comparing maintenance data; and        means for communicating test data to one or more CAM cores.     
     
     
       64. An apparatus for performing built- in self - test  ( BIST )  testing on a content addressable memory  ( CAM )  core, comprising:      means for writing test data to memory addresses in the CAM core;        means for searching for test data in the CAM core, the searching being capable of being continuously performed one cycle after another, or the writing of the test data capable of being performed in a same cycle as one or more search performed during the searching, or combinations thereof, wherein the CAM core is a ternary CAM core.     
     
     
       65. The apparatus as claimed in  claim 64 , further comprising:
   means for selecting one row of the CAM core to be valid during the searching, such that matches occur in the one row in one of the cycles.     
     
     
       66. The apparatus as claimed in  claim 64 , wherein the CAM core comprises one or more words, and one or more of the words includes one or more binary tag bits or a valid bit, or combinations thereof. 
     
     
       67. An apparatus for performing built- in self - test  ( BIST )  testing on a content addressable memory  ( CAM )  core, comprising:      means for enabling searches of the CAM core;        means for enabling addressing of locations of the CAM core, said addressing enabling means further including means for writing to locations of the CAM core; and        means for coordinating BIST testing of the CAM core, said BIST testing coordinating means being capable of performing a BIST search and a BIST write on the CAM core at the same time.