Method for fabricating a semiconductor storage device having an increased dielectric film area

Abstract

A semiconductor device of the present invention is a semiconductor memory having a charge storage film. Recesses or holes which effectively increase the capacitance of a floating gate or a memory cell capacitor are formed in the charge storage film. These recesses or holes are formed at the same time the floating gate electrode or the lower electrode of the capacitor is isolated into the form of islands. A dielectric film and a polysilicon film is formed on the isolated island floating gate electrodes or lower electrodes. These recesses or holes increase the surface area of the dielectric film and improve the write and erase characteristics of a memory cell.

1. A method of fabricating a semiconductor device, comprising:
 the first step of defining an element active region by forming an element isolation structure on a semiconductor substrate;  
 the second step of forming an insulating film on said semiconductor substrate in said element active region;  
 the third step of forming a first conductive film on an entire surface of said semiconductor substrate including said insulating film, and said element isolation structure;  
 the fourth step of forming a mask pattern having first and second openings on said first conductive film;  
 the fifth step etching said first conductive film until said element isolation structure is exposed in said first opening by using said mask pattern as a mask, thereby dividing said first conductive film, and simultaneously forming a recess in said second opening where said first conductive film forms a bottom of said recess;  
 the sixth step of forming a dielectric film so as to cover a surface of said firs conductive film; and  
 the seventh step of forming a second conductive film on said dielectric film opposing said first conductive film through said dielectric film.  
 
     
     
       2. A method according to  claim 1 , further comprising, after the seventh step, the eighth step of doping an impurity into said semiconductor substrate in said element active region to form a pair of impurity diffusion layers in surface regions of said semiconductor substrate on two sides of said first conductive film. 
     
     
       3. A method according to  claim 1 , wherein in the fourth step, said mask pattern is so formed that a width of said first opening is not less than twice a width of said second opening. 
     
     
       4. A method according to  claim 1 , further comprising, between the third and fourth steps, the ninth step of planarizing said first conductive film by polishing, and
 wherein in the fourth step, said mask pattern is so formed that said second opening is positioned above said element active region.  
 
     
     
       5. A method of fabricating a semiconductor device, comprising:
 the first step of forming a first conductive film in an insulating film region on a semiconductor substrate;  
 the second step of forming a mask pattern having first and second openings of different dimensions on said first conductive film;  
 the third step of etching said first conductive film by using said mask pattern as a mask, thereby dividing said first conductive film conforming to a shape of said first opening so as to reach said insulating film region, and simultaneously forming a cylindrical hole below said second opening in which a surface of said insulating film region is exposed in a surface of said divided first conductive film conforming to a shape of the other opening;  
 the fourth step of forming an insulating film so as to cover a surface of said first conductive film; and  
 the fifth step of forming a second conductive film so as to cover a surface of said insulating film opposing said first conductive film through said insulating film.  
 
     
     
       6. A method according to  claim 5 , wherein in the third step, said recess is so formed as to reach said insulating film region, thereby forming a hole in which a surface of said insulating film region is exposed. 
     
     
       7. A method of fabricating a semiconductor device, comprising:
 the first step of defining an element active region by forming an element isolation structure on a semiconductor substrate;  
 the second step of forming an insulating film on said semiconductor substrate in said element active region;  
 the third step of forming a first conductive film on an entire surface including said insulating film and said element isolation structure;  
 the fourth step of forming a mask pattern having at least first and second openings on said first conductive film;  
 the fifth step of etching said first conductive film until said element isolation structure is exposed in said first and second openings by using said mask pattern as a mask, thereby dividing said first conductive film below said first opening, and simultaneously forming a cylindrical hole extending through said first conductive film below said second opening and said first conductive film is etched until said insulating layer is exposed in said first opening;  
 the sixth step of forming a dielectric film so as to cover said first conductive film; and  
 the seventh step of forming a second conductive film on said dielectric film and opposing said first conductive film through said dielectric film.  
 
     
     
       8. A method according to  claim 7 , further comprising, after the seventh step, the eight  eighth step of doping an impurity into said semiconductor substrate in said element active region to form a pair of impurity diffusion layers in surface regions of said semiconductor substrate on two sides of said first conductive film. 
     
     
       9. A method according to  claim 7 , further comprising, between the third and fourth steps, the ninth step of planarizing said first conductive film by polishing. 
     
     
       10. A method according to  claim 7 , wherein in the first step, a field shield element isolation structure in which a shield plate electrode is embedded is formed on said semiconductor substrate. 
     
     
       11. A method of fabricating a semiconductor substrate, comprising:
 the first step of defining an element active region by forming an element isolation structure on a semiconductor substrate;  
 the second step of forming a gate oxide film and a gate electrode on said semiconductor substrate in said element active region;  
 the third step of doping an impurity into said semiconductor substrate in said element active region to form a pair of impurity diffusion layers in surface regions of said semiconductor substrate on two sides of said gate electrode;  
 the fourth stop  step of forming an insulating interlayer on an entire surface of said semiconductor substrate;  
 the fifth step of forming a hole in said insulating interlayer in which one of said impurity diffusion layers is exposed;  
 the sixth step of forming a first conductive film on said insulating interlayer which fills said hole electrically connected to one of said impurity diffusion layers;  
 the seventh step of forming a mask pattern having at least first and second openings on said first conductive film;  
 the eighth step of etching said first conductive film by using said mask pattern as a mask, thereby dividing said first conductive film below said first opening, and simultaneously forming a cylindrical hole extending through said first conductive film below said second opening, said first conductive film is etched until said insulating interlayer is exposed in said first opening;  
 the ninth step of forming a dielectric film so as to cover a surface of said first conductive film; and  
 the tenth step of forming a second conductive film so as to cover said dielectric film opposing said first conductive film through said dielectric film.  
 
     
     
       12. A method according to  claim 11 , further comprising, between the sixth and seventh steps of planarizing said first conductive film by polishing. 
     
     
       13. A method according to  claim 11 , wherein in the first step, a field shield element isolation structure in which a shield plate electrode is embedded is formed on said semiconductor substrate. 
     
     
       14. A method of fabricating a semiconductor device, comprising:
   forming a conductive film on a surface of an element isolation structure formed on a semiconductor substrate and on a surface of an insulating film formed in element active regions defined by the element isolation structure;        forming a mask pattern having at least first and second openings on the first conductive film; and        etching the conductive film until the element isolation structure is exposed through the first opening in the mask pattern, and simultaneously etching the conductive film through the second opening in the mask pattern to form a recess in which the conductive film forms a bottom of the recess.     
     
     
       15. The method of  claim 14 , further comprising forming a dielectric film on a surface of the conductive film. 
     
     
       16. The method of  claim 15 , further comprising forming a second conductive film on a surface of the dielectric film. 
     
     
       17. The method of  claim 16 , wherein the second conductive film opposes the conductive film through the dielectric film. 
     
     
       18. The method of  claim 14 , further comprising doping an impurity into the semiconductor substrate in the element active regions to form a pair of impurity diffusion layers in surface regions of the semiconductor substrate on two sides of the conductive film. 
     
     
       19. The method of  claim 14 , wherein the mask pattern is formed so that a width of the first opening is not less than twice a width of the second opening. 
     
     
       20. The method of  claim 14 , further comprising planarizing the conductive film by polishing after forming the conductive film. 
     
     
       21. The method of  claim 14 , further comprising forming the mask pattern so that the second opening is positioned above at least one of the element active regions. 
     
     
       22. A method of fabricating a semiconductor device, comprising:
   forming a conductive film on a surface of an element isolation structure formed on a semiconductor substrate and on a surface of an insulating film formed in element active regions defined by the element isolation structure;        forming a mask pattern having at least first and second openings on the conductive film; and        etching the conductive film until the element isolation structure is exposed through the first opening in the mask pattern, and simultaneously etching the conductive film through the second opening in the mask pattern to form a cylindrical hole in the conductive film below the second opening.     
     
     
       23. The method of  claim 22 , further comprising simultaneously etching the conductive film through a third opening in the mask pattern to form a recess in which the conductive film forms a bottom of the recess. 
     
     
       24. The method of  claim 22 , further comprising forming a dielectric film on a surface of the conductive film. 
     
     
       25. The method of  claim 24 , further comprising forming a second conductive film on a surface of the dielectric film. 
     
     
       26. The method of  claim 22 , further comprising etching the conductive film so that the cylindrical hole formed below the second opening exposes the element isolation structure. 
     
     
       27. The method of  claim 22 , further comprising etching the conductive film so that a cylindrical recess is formed below the second opening in which the conductive film forms a bottom of the cylindrical recess. 
     
     
       28. The method of  claim 22 , further comprising planarizing the conductive film by polishing after forming the conductive film. 
     
     
       29. A method of fabricating a semiconductor device, comprising:
   forming a gate electrode in an element active region defined by an element isolation structure formed on a semiconductor substrate;        doping an impurity into the semiconductor substrate in the element active region to form a pair of impurity diffusion layers in surface regions of the semiconductor substrate on two sides of the gate electrode;        forming an insulating interlayer on a surface of the element active region and a surface of the element isolation structure;        forming a hole in the insulating interlayer in which one of the impurity diffusion layers is exposed;        forming a conductive film on a surface of the insulating interlayer, wherein the conductive film fills the hole to electrically connect to the impurity diffusion layer;        forming a mask pattern having at least first and second openings on the conductive film; and        etching the conductive film until the insulating interlayer is exposed through the first opening in the mask pattern, and simultaneously exposing the insulating interlayer by etching the conductive film through the second opening in the mask pattern to form a cylindrical hole in the conductive film  below the second opening .    
     
     
       30. The method of  claim 29 , further comprising simultaneously etching the conductive film through a third opening in the mask pattern to form a recess in which the conductive film forms a bottom of the recess. 
     
     
       31. The method of  claim 29 , further comprising forming a dielectric film on a surface of the conductive film. 
     
     
       32. The method of  claim 31 , further comprising forming a second conductive film on a surface of the dielectric film. 
     
     
       33. The method of  claim 29 , further comprising planarizing the conductive film by polishing after forming the conductive film.