Low dropout regulator capable of on-chip implementation

Abstract

A low-dropout regulator comprises a high-gain error amplifier having a differential input stage and a single-ended output, a high-swing high-positive-gain second stage with input connecting to the output of the error amplifier and a single-ended output, a p-type MOS transistor with gate terminal connecting to the output of the second stage, source terminal connecting to the supply voltage, and drain terminal to the output of the low-dropout regulator. A first-order high-pass feedback network connects the output of the low-dropout regulator and the positive input of the error amplifier, and a damping-factor-control means comprising a negative gain stage with a feedback capacitor connects the input and output of this gain stage. A capacitor is connected between the output of the error amplifier and the output of the low-dropout regulator, while a voltage reference connects to the negative input of the error amplifier. The regulator does not require an off-chip capacitor for stability and has improved load transient response and power supply rejection ratio.

1. A low-dropout regulator comprising:
 a high-gain error amplifier having a differential input stage and a single-ended output  
 a high-swing high-positive-gain second stage with input connecting to the output of the error amplifier and a single-ended output  
 a p-type MOS transistor with gate terminal connecting to the output of the second stage, source terminal connecting to the supply voltage, and drain terminal to the output of the low-dropout regulator  
 a first-order high-pass feedback network connecting to the output of the low-dropout regulator and the positive input of the error amplifier  
 a damping-factor-control means comprising a negative gain stage with a feedback capacitor connecting between the input and output of this gain stage, wherein the damping- factor - control means is coupled to the error amplifier or to the second stage;    
 a capacitor connecting between the output of the error amplifier and the output of the low-dropout regulator  
 a voltage reference connecting to the negative input of the error amplifier.  
 
     
     
       2. A low-dropout regulator as claimed in  1  wherein said the second stage is in common-source configuration. 
     
     
       3. A low-dropout regulator as claimed in  1  wherein said the p-type MOS transistor operates in either linear or saturation region. 
     
     
       4. A low-dropout regulator as claimed in  1  wherein said the first-order high-pass feedback network comprises two resistors connecting in series, one of said resistors being connected between the output of LDO  the low- dropout regulator  and the positive input of the error amplifier, and the other said resistor being connected between the positive input of the error amplifier and the ground, and wherein a capacitor is connected between the output of LDO  the low- dropout regulator  and the positive input of the error amplifier. 
     
     
       5. A low-dropout regulator as claimed in  4  wherein said the first-order high-pass feedback network creates a left-half-plane zero and a left-half-plane pole. 
     
     
       6. A low-dropout regulator as claimed in  5  wherein said the first-order high-pass feedback network provides that the frequency of the left-half-plane zero is lower than the frequency of the left-half-plane pole. 
     
     
       7. A low-dropout regulator as claimed in  1  wherein said the damping-factor-control means is a gain stage with voltage gain larger than one. 
     
     
       8. A low-dropout regulator as claimed in  1  wherein said the damping-factor-control means includes circuitry to define the output voltage level. 
     
     
       9. A low-dropout regulator as claimed in  1  wherein said the damping-factor-control means includes a high-swing common-source output stage. 
     
     
       10. A low-dropout regulator as claimed in  1  wherein said the damping-factor-control means provides a pole-splitting effect. 
     
     
       11. A low-dropout regulator as claimed in  1  wherein said the damping-factor-control means locates a pole at a low frequency while locating the second and third poles at high frequency. 
     
     
       12. A low-dropout regulator as claimed in  1  wherein said the damping-factor-control means locates the second and third poles at high frequency and the poles can in separate form or complex form. 
     
     
       13. A low-dropout regulator as claimed in  1  wherein said the damping-factor-control means is connected at the  an output of the second gain stage. 
     
     
       14. A low-dropout regulator as claimed in  1  wherein said the low-dropout regulator is stabilized with an off-chip capacitor. 
     
     
       15. A low-dropout regulator as claimed in  1  wherein said the low-dropout regulator is stabilized without an off-chip capacitor. 
     
     
       16. A low-dropout regulator as claimed in  14  wherein said the low-dropout regulator has four poles and two zeros when the off-chip capacitor is connected at the output of the low-dropout regulator. 
     
     
       17. A low-dropout regulator as claimed in  16  wherein said the low-dropout regulator uses the two zeros cancel the effect of the second and third poles while keeping the fourth pole after the unity-gain frequency of the loop gain. 
     
     
       18. A low-dropout regulator as claimed in  15  wherein said low-dropout regulator has two poles and one zero when no off-chip capacitor is connected at the output of the low-dropout regulator. 
     
     
       19. A low-dropout regulator as claimed in  18  wherein said the low-dropout regulator uses the zero to cancel the effect of the second pole. 
     
     
       20. A low-dropout regulator as claimed in  1  wherein said the voltage reference is a circuit that provides a supply- and temperature-independent voltage to define the output voltage of the low-dropout regulator. 
     
     
       21. A low-dropout regulator as claimed in  1  wherein said the low-dropout regulator is implemented in an integrated-circuit technology or discrete-component implementation. 
     
     
       22. A low-dropout regulator comprising a three-stage amplifier formed of (a) a high-gain error amplifier, (b) a high-swing high-positive gain second stage and (c) a p-type MOS transistor the gate terminal of which is connected to the  an output of said second stage, wherein said regulator further comprises damping-factor-control means connected to the  an output of the said error amplifier, wherein the damping- factor - control means comprises a negative gain stage.    
     
     
       23. A low-dropout regulator comprising a three-stage amplifier formed of (a) a high-gain error amplifier, (b) a high-swing high-positive gain second stage and (c) a p-type MOS transistor the gate terminal of which is connected to the  an output of said second stage, wherein said regulator further comprises damping-factor-control means connected to the output of the said second stage, wherein the damping- factor - control means comprises a negative gain stage.    
     
     
       24. An integrated circuit, comprising:
   an error amplifier;        a high - swing high - positive - gain stage including an input terminal coupled to an output terminal of the error amplifier;        a transistor including a gate terminal coupled to an output terminal of the high - swing high - positive - gain stage; and        a damping - factor - control circuit including a negative gain stage and a feedback capacitor, wherein the damping factor - circuit is coupled to the output terminal of the high - swing high - positive gain stage or to the error amplifier.      
     
     
       25. The integrated circuit of  claim 24 , further comprising a voltage reference circuit coupled to a negative input terminal of the error amplifier.  
     
     
       26. The integrated circuit of  claim 24 , further comprising a capacitor disposed between the output terminal of the error amplifier and a regulator output terminal of the integrated circuit.  
     
     
       27. The integrated circuit of  claim 24 , further comprising a first- order high - pass feedback network coupled to a regulator output terminal of the integrated circuit and a positive input terminal of the error amplifier.    
     
     
       28. The integrated circuit of  claim 28 , wherein the first- order high - pass feedback network comprises a first resistor coupled between the regulator output terminal of the integrated circuit and the positive input terminal of the error amplifier and a second resistor coupled between the positive input terminal of the error amplifier and ground, and wherein the integrated circuit further comprises a capacitor disposed between the regulator output terminal and the positive input terminal of the error amplifier.    
     
     
       29. The integrated circuit of  claim 29 , wherein the first- order high - pass feedback network is configured to create a left - half - plane zero and a left - half - plane pole.    
     
     
       30. The integrated circuit of  claim 30 , wherein the first- order high - pass feedback network is configured to provide a frequency of the left - half - plane zero that is lower than a frequency of the left - half - plane pole.    
     
     
       31. The integrated circuit of  claim 24 , wherein the damping- factor - control circuit is coupled to the output terminal of the error amplifier.    
     
     
       32. The integrated circuit of  claim 24 , wherein the damping- factor - control circuit comprises a high - swing common - source output terminal stage.    
     
     
       33. The integrated circuit of  claim 24 , wherein the damping- factor - control circuit is configured to provide a pole - splitting effect.    
     
     
       34. An integrated circuit, comprising:
   an error amplifier;        a high - swing high - positive - gain stage including an input terminal coupled to an output terminal of the error amplifier;        a transistor including a gate terminal coupled to an output terminal of the high - swing high - positive - gain stage; and        a damping - factor - control circuit coupled to the error amplifier or to the high - swing high - positive - gain stage, wherein the damping - factor - control circuit is configured to locate a first pole at a first frequency and to locate a second pole and a third pole at a second frequency higher than the first frequency.      
     
     
       35. The integrated circuit of  claim 34 , wherein the error amplifier comprises a high- gain error amplifier, and wherein the error amplifier comprises a differential - input stage and a single - ended output terminal.    
     
     
       36. The integrated circuit of  claim 35 , wherein the transistor is a p- type transistor, and wherein the p - type transistor is coupled to a regulator output terminal of the integrated circuit.    
     
     
       37. The integrated circuit of  claim 35 , wherein the high- swing high - positive - gain stage comprises a common - source configuration.    
     
     
       38. The low- dropout regulator of    claim 23   , wherein the damping - factor control means further comprises a feedback capacitor coupled to the output of the high - swing high - positive gain second stage.