Apparatus for operating a CMOS imager having a pipelined analog to digital converter

Abstract

An image sensor system using offset analog to digital converters. The analog to digital converters require a plurality of clock cycles to carry out the actual conversion. These conversions are offset in time from one another, so that at each clock cycle, new data is available.Systems are disclosed in which an image sensor converts an analog signal into a digital signal using a pipelined analog to digital converter.

1. An analog-to-digital (A/D) converter, comprising:
 an input, for receiving a series of analog signals;    an output, for outputting a series of digital signals respectively corresponding to said series of analog signals;    a plurality of A/D cells, each of said A/D cells for converting one of said series of analog signals to a corresponding one of said series of digital signals; and    a control circuit, coupled to said input, said output, and said plurality of A/D cells;    wherein said control circuit operates said input, said output, and said plurality of A/D cells so that each successive A/D cell is assigned, at a different time, to convert a different one of each successive analog signal from said series of analog signals to a corresponding digital signal in said series of digital signals.    
     
     
       2. The analog-to-digital converter of  claim 1 , wherein said different time correspond to a different period of a clock signal provided to said analog-to-digital converter. 
     
     
       3. The analog-to-digital converter of  claim 1 , wherein each of said A/D cells further comprises a calibration element, said calibration element being set so that each A/D cell coverts the same analog signal present at said input to a same digital value at said output. 
     
     
       4. The analog-to-digital converter of  claim 1 , wherein each of said A/D cells further comprises a noise suppression element. 
     
     
       5. The analog-to-digital converter of  claim 4 , wherein said noise suppression element comprises a transistor. 
     
     
       6. The analog-to-digital converter of  claim 1 , wherein each A/D cell performs an A/D conversion in a same amount of time. 
     
     
       7. The analog-to-digital converter of  claim 1 , wherein each A/D cell performs an A/D conversion using successive approximation. 
     
     
       8. The analog-to-digital converter of  claim 1 , wherein said control circuit operates to cause said analog-to-digital converter to begin converting a different one of said series of analog signals on each of a series of successive clock signals. 
     
     
       9. The analog-to-digital converter of  claim 1 , wherein said control circuit operates to cause said analog-to-digital converter to output a series of digital signals on each of a series of successive clock signals. 
     
     
       10. A method for converting a series of analog signals to a corresponding series of digital signals, comprising:
 receiving over a period of time, a series of analog signals;    assigning each analog signal from said series of analog signals as they are received to an available A/D cell for analog-to-digital conversion to a corresponding digital signal; and    outputting a different digital signal corresponding to a respective analog signal from said series of analog signals as each A/D cell finishes its analog-to-digital conversion;    wherein at least two A/D cells are performing respective analog-to-digital conversions while another A/D cell outputs one of said digital signals.    
     
     
       11. The method of  claim 10 , further comprising:
 calibrating each A/D cell so that an analog-to-digital conversion performed on a same analog signal by any A/D cell results in a same digital signal.    
     
     
       12. The method of  claim 10 , wherein said step of assigning comprises a step of suppressing comparator kickback noise during said analog-to-digital conversion. 
     
     
       13. The method of  claim 10 , wherein each A/D cell performs an analog-to-digital conversion in a same amount of time. 
     
     
       14. The method of  claim 10 , wherein each A/D cell perform an analog-to-digital conversion using successive approximation. 
     
     
       15. A system comprising:
   an input to receive light that forms an image;        an array of photoreceptors of a CMOS active pixel sensor to convert the image into a plurality of successive analog signals;        an analog to digital  ( A/D )  converter comprising a plurality of successive approximation A/D converter cells; and        a controller to assign each of the plurality of successive analog signals to the A/D converter, wherein the A/D converter is configured to convert each of the plurality of successive analog signals to a respective each of a plurality of successive digital signals during time periods that are offset and partially overlapping.     
     
     
       16. The system of  claim 15 , wherein each of the plurality of successive analog signals represents a respective pixel of the image. 
     
     
       17. The system of  claim 16 , wherein the A/D converter is disposed on the same chip as the photoreceptors. 
     
     
       18. The system of  claim 17 , wherein each of the time periods are offset by one clock cycle. 
     
     
       19. The system of  claim 15 , wherein the A/D converter is disposed on the same chip as the photoreceptors, and the photoreceptors are photodiodes. 
     
     
       20. A camera having a lens to receive and focus light, the camera further comprising:
   an array of photoreceptors of a CMOS active pixel sensor to convert the focused light into a plurality of successive analog signals;        an analog to digital  ( A/D )  converter comprising a plurality of A/D converter cells; and        a controller to assign a respective analog signal of the plurality of successive analog signals to the A/D converter at staggered times that are offset from each other, wherein the A/D converter is configured to convert each respective analog signal of the plurality of successive analog signals to a respective digital signal during time periods that are at least partially overlapping.     
     
     
       21. The camera of  claim 20 , wherein the respective digital signal comprises at least a respective first bit. 
     
     
       22. The camera of  claim 21 , wherein the respective digital signal comprises ten bits. 
     
     
       23. The camera of  claim 20 , wherein each of the plurality of A/D converter cells is a successive approximation A/D converter cell. 
     
     
       24. The camera of  claim 23 , wherein the staggered times are offset by one clock cycle. 
     
     
       25. The camera of  claim 20 , wherein the staggered times are offset by one clock cycle. 
     
     
       26. A system comprising:
   an apparatus to receive light and to form an image therefrom;        an array of pixels disposed on a semiconductor substrate to generate electrical signals associated with the image;        an input to an analog to digital (A/D) conversion unit to receive a plurality of analog signals associated with the image; and        an output from the A/D conversion unit to provide a plurality of digital signals corresponding to the analog signals during a second period of time after the first period of time, wherein between the first and second periods of time the A/D conversion unit is to contain different numbers of bits of respective portions of the digital signals corresponding to the analog signals in different states of conversion.     
     
     
       27. The system of  claim 26 , wherein the plurality of digital signals comprises at least three digital signals corresponding to at least three respective analog signals. 
     
     
       28. The system of  claim 27 , further comprising an amplifier to amplify the plurality of analog signals before the analog signals are to be received by the A/D conversion unit. 
     
     
       29. The system of  claim 26 , further comprising an amplifier to amplify the plurality of analog signals before the analog signals are to be received by the A/D conversion unit. 
     
     
       30. A system comprising:
   a conversion circuit comprising a pixel array disposed on a semiconductor substrate and oriented to receive light associated with an image, the conversion circuit configured to convert the light into successive analog signals;        a gain circuit, disposed on the substrate, coupled to the conversion circuit to receive the successive analog signals from the conversion circuit and to amplify the successiive analog signals; and        an analog to digital (A/D) conversion circuit, disposed on the substrate, coupled to the gain circuit to receive the successive analog signals from the gain circuit during a first time period and to convert the successive analog signals into corresponding successive digital signals, wherein the A/D conversion circuit is to determine at least some bits of the corresponding successive digital signals during a second time period that begins after the first time period ends.     
     
     
       31. The system of the  claim 30 , wherein the successive analog signals comprises at least three analog signals.