Non-volatile memory comprising means for distorting the output of memory cells

Abstract

The present invention relates to a non-volatile memory comprising a memory array comprising functional memory cells and non-functional memory cells linked to at least one non-functional word line. A word line address decoder comprises a special decoding section linked to the non-functional word line, for selecting the non-functional word line when a functional word line is read-selected, such that non-functional memory cells are selected simultaneously with the functional memory cells, and distort the reading of the functional memory cells. Application particularly to integrated circuits for smart cards.

1. A method for interfering with the  a reading of data in a plurality of functional memory cells of a non-volatile  memory array, where the functional memory cells are linked  coupled to functional word lines and to bit lines, the bit lines being linked  coupled to sense amplifiers, and wherein the  a value of a datum read by a sense amplifier in a  the respective functional memory cell varies according to the  an on or an off state of the respective functional memory cell, which itself  state varies according to the  a programmed or an erased state  condition of the respective functional memory cell, the method comprisingthe steps of :
 providing a plurality of non-functional memory cells linked  coupled to the bit lines of the memory array and to at least one non-functional  word line for enabling the non-functional memory cells to be selected, and  
 whenwhile the functional memory cells are read-selected, simultaneously  selecting non-functional memory cells, such that the non-functional memory cells that are in the on state interfere with the  distort reading of the functional memory cells that are in the off state,  and cause the supply of distorted logic values at output of the sense amplifiers.  
 
     
     
       2. The method of  claim 1 , further comprising the step of  providing a word line address decoder including a special decoding section linked  coupled to the non-functional word line, for applying a selection signal to the non-functional word line when  while a functional word line is read-selected by the word line address decoder. 
     
     
       3. The method of  claim 2 , further comprising the step of  providing a special decoding section that is activated by a distortion enabling signal, the non-functional memory cells not being selected while the special decoding section is not activated. 
     
     
       4. The method of  claim 3 , farther comprising the step of  providing a register for storing a distortion enabling bit the  having a value of which  that determines the  a value of the distortion enabling signal. 
     
     
       5. The method of  claim 1 , further comprising a step of assign  assigning all of the non-functional memory cells a determined programmed or erased state  condition, so that all of the non-functional memory cells are in the on state when they are selected, so as to distort the  reading of all of the  corresponding functional memory cells in the off state. 
     
     
       6. The method of  claim 1 , further comprising a step of  assigning only one part  at least one non- functional memory cell  of the plurality of non-functional memory cells a determined programmed or erased state, so that the at least one non-functional memory cells are  is in the on state when they are  the at least one non- functional memory cell is  selected, so as to distort the  a respective reading of only one part  at least one of the functional memory cells. 
     
     
       7. The method of  claim 1  wherein the  at least one of said at least one non-functional word line is interspersed with the functional word lines, and is configured in a location that can correspond to that of a functional word line. 
     
     
       8. The method of  claim 1 , further comprising the step of  providing non-functional memory cells, each one of the non- functional memory cells  having the same  a structure as the  that is the same as a structure of a corresponding functional memory cells and which cannot be visually distinguished from the latter  cell. 
     
     
       9. The method of  claim 1 , further comprising providing non-functional memory cells comprising transistors having a drain-source short-circuit. 
     
     
       10. A non-volatile memory comprising:
   a word line address decoder;   
 a memory array comprising  having functional memory cells linked  coupled to functional word lines and to bit lines, the bit lines being linked to sense amplifiers,  the word lines being linked  coupled to a  the word line address decoder, the  a value of a datum read by a sense amplifier in  from at least a respective functional memory cell varying according to the  an on or an off state of the respective functional memory cell, which itself varies according to the  one of a programmed or an erased state of the memory cell, a memory comprising: ; 
 a plurality of non-functional memory cells linked  coupled to the bit lines of the memory array and to at least one non-functional word line, and  
 the word line address decoder including a special decoding section linked  coupled to the non-functional word line, configured to select the at least one non-functional word line when a respective functional word line is read-selected, such that non-functional memory cells are selected simultaneously with the functional memory cells being selected and distorting the reading of the functional memory cells.  
 
     
     
       11. The memory of  claim 10 , where  wherein the special decoding section of the word line address decoder is configured to be activated by a distortion-enabling signal, the non-functional memory cells not being selected while the special decoding section is not activated. 
     
     
       12. The memory of claim  10    11 , further comprising a register for storing a distortion-enabling bit the  having a value of which  that determines the  a value of the distortion-enabling signal. 
     
     
       13. The memory of  claim 10 , further comprising: 
 a  means for erasing and programming the non-functional memory cells, ;  
   means for  enabling non-functional memory cells to be selectively put into a determined erased or programmed state, such that the non-functional memory cells are active when they are selected .  
 
     
     
       14. The memory of  claim 10  wherein the word line address decoder is configured to receive an extended word line address comprising at least one extra address bit relative to the  a number of address bits that the addressing of  required to address the functional word linesrequires , and individually erase or program selects the  each non-functional word line selected when an  a respective extended address of predetermined value is applied to it. 
     
     
       15. The memory of  claim 10 , comprising a central processing unit configured to decode and execute an instruction for programming or erasing non-functional memory cells. 
     
     
       16. The memory of  claim 10  wherein the  at least one non-functional word line is interspersed with the functional word lines, and is configured in a location that can correspond to that of a functional word line. 
     
     
       17. The memory of  claim 10  wherein the non-functional memory cells have the same structure as  and the functional memory cells have respective structures that are the same, and the structure of the non- functional memory cells  cannot be visually distinguished from the latter  structure of the functional memory cells. 
     
     
       18. The memory of  claim 10  wherein the non-functional memory cells further comprise transistors having a drain-source short-circuit. 
     
     
       19. An integrated circuit comprising:
   a word line address decoder;    
 a memory according to  claim 10   array having functional memory cells coupled to functional word lines and to bit lines, the word lines being coupled to the word line address decoder, a value of a datum read from a respective functional memory cell varying according to an on or an off state of the respective functional memory cell, which itself varies according to one of a programmed or an erased state of the memory cell,  
   a plurality of non - functional memory cells coupled to the bit lines of the memory array and to at least one non - functional word line, and    
   a special decoding section in the word line address decoder configured to read - select the at least one non - functional word line at the same time a respective functional word line is read - selected .  
 
     
     
       20. The integrated circuit of  claim 19 , comprising means for activating the special decoding section of the word line address decoder when a prohibited event occurs in the integrated circuit, such that data present in the memory array are read-accessible in a distorted form only. 
     
     
       21. A smart card, comprising:
   a housing;    
   data input and output signal lines within the housing;   
 an integrated circuit according to  claim 19   having a memory, the memory including, 
   a word line address decoder;    
   a plurality of functional word lines coupled to the word line address decoder;    
   a non - functional word line coupled to the word line address decoder;    
   a memory array having functional memory cells coupled to the functional word lines and to bit lines, the word lines being coupled to the word line address decoder, a value of a datum read from a respective functional memory cell varying according to an on or an off state of the respective functional memory cell, which itself varies according to one of a programmed or an erased state of the memory cell,    
   a plurality of non - functional memory cells coupled to the bit lines of the memory array and to the non - functional word line, and    
   a special decoding section in the word line address decoder configured to select the non - functional word line at the same time a functional word line is read - selected to couple both functional and non - functional memory cells to the same bit line during a read .  
 
 
     
     
       22. A memory device comprising:
 a plurality of first memory cells configured to store data; and  
 a second memory cell configured to output misleading data bits for distorting data stored in at least  as it is being read from one of the first memory cells, during an unauthorized attempt to read the memory device, the second memory cell including at least one transistor having a drain and a source coupled to the drain.  
 
     
     
       23. The memory device of  claim 22  wherein the second memory cell is programmable to an on or off state. 
     
     
       24. The memory device of  claim 23  wherein the second memory cell includes at least one non-volatile transistor. 
     
     
       25. A smart card comprising:
 a plurality of first memory cells configured to store data;  
 aat least one second memory cell configured to output a bit of misleading data bitsdatum to a word, the word consisting ofcomprising data stored in at least one of the first memory cells, during an unauthorized attempt to read the data stored in the smart card; and  
 logic configured to disable the at least one second memory cell until an unauthorized attempt to read the smart card is detected, the at least one second memory cell being comprised of at least one dummy transistor, and the at least one dummy transistor having: 
 a source; and  
 a drain coupled to the source.  
 
 
     
     
       26. The smart card of  claim 25  wherein the second memory cell includes at least one non-volatile transistor. 
     
     
       27. A memory device comprising:
 a plurality of first memory cells configured to store data;  
 a second memory cell configured to output misleading data bits to a word, the word consisting of data stored in at least one of the first memory cells, during an unauthorized attempt to read the memory device;  
 the first memory cells coupled to  a plurality of first word linesand , each one of the first word lines having a first number of the plurality of first memory cells coupled thereto; 
 a plurality of bit lines, each one of the bit lines having a second number of the plurality of first memory cells coupled thereto, wherein each one of the first memory cells is coupled to a respective first word line and a respective bit line; 
 a plurality of the second memory cells coupled to a second word line each of the second memory cells also being coupled to at least one of the bit lines;  
 an address decoder configured to select word lines to be read; and  
 logic associated with the address decoder configured to read  select the second word line to be read during an unauthorized read attempt of data stored in the first plurality of memory cells.  
 
     
     
       28. The memory device of  claim 27  further comprising:
 an extended address, and  
 logic within the address decoder configured to distinguish an unauthorized read attempt based on the status of a bit within an extended address.  
 
     
     
       29. The memory device of  claim 27  wherein the second memory cell includes at least one non-volatile transistor. 
     
     
       30. A memory device comprising:
 a first functional memory cell linked  coupled to a first bit line;  
 a first non-functional memory cell linked  coupled to the first bit line; and  
 selective memory cell reading means, linked  coupled to the first bit line, for simultaneously  reading the first functional memory cell and  the first non-functional memory cell while reading the first functional memory cell when an unauthorized attempt to read the memory device is detected.  
 
     
     
       31. The memory device of  claim 30  wherein the selective memory cell reading means includes a sense amplifier. 
     
     
       32. The memory device of  claim 30  wherein the selective memory cell reading means includes logic to disable the first non-functional memory cell until the unauthorized attempt to read the memory device is detected. 
     
     
       33. The memory device of  claim 32  wherein while the first non-functional memory cell is disabled, the selective memory cell reading means reads only the first functional memory cell. 
     
     
       34. The memory device of  claim 30  wherein the first functional memory cell has a bit of data stored therein, the bit of data having a given value, wherein the first non-functional memory cell provides an output to the selective memory cell reading means when the unauthorized attempt to read the memory device is detected, and the selective memory cell reading means provides an output based upon the given value of the bit of data and the output of the first non-functional memory cell, the output of the selective memory cell reading means being different from the given value of the bit of data. 
     
     
       35. The memory device of  claim 30  wherein in response to detecting the unauthorized attempt to read the memory device, the selective memory cell reading means permanently reads the first functional memory cell and the first non-functional memory cell. 
     
     
       36. A memory device comprising:
   a plurality of word lines;        a plurality of bit lines;        a plurality of memory cells, each memory cell coupled to a respective word line of the plurality of word lines and coupled to a respective bit line of the plurality of bit lines; and        a word line selector circuit configured to select a respective first word line of the plurality of word lines during an authorized read of a number of memory cells coupled to the respective first word line and to select the respective first word line and a respective second word line of the plurality of word lines during an unauthorized read of the number of memory cells coupled to the respective first word line.     
     
     
       37. The memory device of  claim 36  wherein the word line selector circuit includes:
   a word line decoder configured to select the respective first word line for a respective authorized or unauthorized read of the number of memory cells coupled to the respective first word line; and    
   a special decoding section configured to select the respective second word line during a respective unauthorized read of the number of memory cells coupled to the respective first word line.   
 
     
     
       38. The memory device of  claim 37  wherein the word line selector circuit is configured to receive an extended word line address having a first number of address bits and a second number of address bits, wherein the word line decoder is configured to address the respective first word line from the first number of address bits, and wherein the special decoding section is configured to address the respective second word line from the second number of bits. 
     
     
       39. The memory device of  claim 37  wherein the special decoding section is activated by a distortion- enabling signal, and the special decoding section does not select the respective second word line when the special decoding section is not activated.   
     
     
       40. The memory device of  claim 39 , further comprising:
   a register that stores a distortion - enabling bit having a value that determines a value of the distortion - enabling signal.     
     
     
       41. The memory device of  claim 36  wherein the word line selector means includes:
   means for erasing and programming the number of memory cells coupled to the respective first word line;    
   means for enabling at least one memory cell coupled to the respective second word line to be selectively put into a determined erased or programmed state, such that the at least one memory cell coupled to the respective second word line is active when selected.   
 
     
     
       42. The memory device of  claim 36  wherein the word line selector means includes a processing unit configured to decode and execute an instruction for programming or erasing at least one memory cell coupled to the respective second word line. 
     
     
       43. The memory device of  claim 36  wherein the at least one memory cell coupled to the respective second word line includes at least one transistor having a drain- source short - circuit.   
     
     
       44. The memory device of  claim 36  further comprising an integrated circuit having a memory array that includes the plurality of word lines, the plurality of bit lines, the plurality of memory cells and the word line selector means. 
     
     
       45. The memory device of  claim 44  further comprising a smart card having the integrated circuit. 
     
     
       46. The memory device of  claim 36  further comprising logic that disables at least one memory cell coupled to the respective second word line until a respective unauthorized read of the number of memory cells coupled to the respective first word line. 
     
     
       47. The memory device of  claim 36  wherein each memory cell is connected to a respective word line of the plurality of word lines and connected to a respective bit line of the plurality of bit lines. 
     
     
       48. A method for interfering with reading of data stored in a memory array having a plurality of memory cells, a plurality of word lines and a plurality of bit lines, each memory cell coupled to a respective one of the bit lines and also to a respective one of the word lines, comprising:
   selecting a first word line the plurality of word lines to read a first at least one memory cell coupled to the first word line; and        selecting a second word line of the plurality of word lines while selecting the first word line, to read a second memory cell coupled to the second word line while reading the first memory cell in response to an unauthorized read of the first memory cell.     
     
     
       49. The method of  claim 48  wherein selecting a first word line of the plurality of word lines and selecting a second word line of the plurality of word lines includes:
   receiving an extended word line address having a first number of address bits and a second number of address bits, wherein the respective first word line is selected based on the first number of address bits, and wherein the respective second word line is selected based on the second number of bits.   
 
     
     
       50. The method of  claim 48  wherein selecting a second word line of the plurality of word lines includes:
   receiving a distortion - enabling signal.   
 
     
     
       51. The method of  claim 50  further comprising:
   storing a distortion - enabling bit having a value that determines a value of the distortion - enabling signal.   
 
     
     
       52. The method of  claim 48  further comprising:
   disabling the second at least one memory cell coupled to the second word line until the unauthorized read of the first at least one memory cell.   
 
     
     
       53. The method of  claim 48  further comprising:
   erasing and programming the first at least one memory cell coupled to the first word line; and    
   enabling the second at least one memory cell coupled to the second word line to be selectively put into a determined erased or programmed state, such that the at least one memory cell coupled to the respective second word line is active when selected.   
 
     
     
       54. An circuit for outputting incorrect data from a memory array comprising:
   a plurality of memory cells storing correct data;        a plurality of word lines and a plurality of bit lines, each memory cell coupled to a respective one of the bit lines and also to a respective one of the word lines;        means for selecting a first word line the plurality of word lines to read a memory cell coupled to the first word line;        means for selecting a second word line of the plurality of word lines to read a second memory cell coupled to the second word line at the same time the first word line is selected in response to an unauthorized read of data in the memory array;        means for putting a combined signal from a memory cell coupled to the first word line and a memory cell coupled to the second word line on the same bit line during an unauthorized read of the data in the memory array.     
     
     
       55. The memory array of  claim 54  further including:
   means for storing incorrect data into the memory cells coupled to the second word line.