Semiconductor device having metal silicide layer on source/drain region and gate electrode and method of manufacturing the same

Abstract

A semiconductor device includes a semiconductor substrate, an element-isolating region formed in the semiconductor substrate, a real element region formed in the semiconductor substrate and outside the element-isolating region and having a metal silicide layer formed on the surface thereof, and a dummy element region formed in the semiconductor substrate and outside the element-isolating region and having a metal silicide layer formed on the surface thereof. The ratio of the sum of pattern areas of the real element region and dummy element region occupied in a 1 μm-square range of interest including the element region is 25% or more.

1. A semiconductor device comprising:
 a semiconductor substrate;  
 an element-isolating region formed in the semiconductor substrate; and  
 a plurality of element regions formed in the semiconductor substrate and outside the element-isolating region and having a metal silicide layer formed on the surface thereof, said plurality of element regions including a real element region and at least one dummy element region,  
 wherein the ratio of the sum of pattern areas of the real element region and said at least one dummy element region occupied in a 1 μm square range of interest including the element region is 25% or more.  
 
     
     
       2. The semiconductor device according to  claim 1 , wherein each of the real element region and said at least one dummy element region comprises
 a well having a channel region;  
 a first impurity diffusion layer formed in a surface region of the well;  
 a gate electrode formed on the channel region of the well via a gate insulating film; and  
 a metal silicide layer formed on each of the first impurity diffusion layer and the gate electrode.  
 
     
     
       3. The semiconductor device according to  claim 1 , wherein said at least one dummy element region comprises
 a well;  
 a first impurity diffusion layer formed over an entire surface of the surface region of the well; and  
 the metal silicide layer formed on an upper surface of the first impurity diffusion layer.  
 
     
     
       4. The semiconductor device according to  claim 1 , wherein said at least one dummy element region comprises
 a well; and  
 the metal silicide layer formed on the well.  
 
     
     
       5. The semiconductor device according to  claim 1 , wherein said at least one dummy element region comprises
 a well;  
 a second impurity diffusion layer for well contact formed in a surface region of the well; and  
 the metal silicide layer formed on the well and the second impurity diffusion layer.  
 
     
     
       6. The semiconductor device according to  claim 1 , wherein said at least one dummy element region includes a dummy gate electrode. 
     
     
       7. The semiconductor device according to  claim 1 , wherein the metal silicide layer contains either one of metals, Ni and Pt. 
     
     
       8. The semiconductor device according to  claim 1 , wherein the element-isolating region comprises
 a trench formed in the semiconductor substrate; and an insulating film burying within the trench.  
 
     
     
       9. A semiconductor device, comprising:
   a semiconductor substrate;        an element - isolating region formed in the semiconductor substrate; and        a plurality of element regions formed in the semiconductor substrate, isolated by the element - isolating region and having a metal silicide layer, including a real element region and        at least one dummy element region,        wherein a ratio of a sum of an area of the real element region and an area of said at least one dummy element region occupied in a  1  μm square region containing the real element region and at least a portion of said at least one dummy element region is at least  25   %.   
     
     
       10. The semiconductor device according to  claim 9 , comprising:
   a plurality of dummy element regions, wherein portions of a plurality of said dummy element regions are included in said square region, and a ratio of a sum of an area of the real element region to a sum of areas of said portions of said dummy element regions is  25   %  or more.     
     
     
       11. The semiconductor device according to  claim 10 , comprising:
   at least one of said dummy regions having a shape different than a shape of said real element region.     
     
     
       12. The semiconductor device according to  claim 10 , comprising:
   an area of at least one of said dummy regions being larger than an area of said real element region.     
     
     
       13. The semiconductor device according to  claim 9 , comprising:
   at least one of said dummy regions having a shape different than a shape of said real element region.     
     
     
       14. The semiconductor device according to  claim 9 , comprising:
   an area of at least one of said dummy regions being larger than an area of said real element region.     
     
     
       15. The semiconductor device according to  claim 9 , wherein:
   said real element region comprises a first transistor; and        said dummy element region comprises a second transistor.     
     
     
       16. The semiconductor device according to  claim 15 , wherein:
   each of said first and second transistors includes a gate electrode.     
     
     
       17. The semiconductor device according to  claim 9 , wherein at least one of the real element region and said at least one dummy element region comprises:
   a channel region;        a gate electrode formed on the channel region via a gate insulating film;        a diffusion region; and        a metal silicide layer formed on each of the diffusion region and the gate electrode.     
     
     
       18. The semiconductor device according to  claim 9 , wherein said at least one dummy element region comprises a well, and the metal silicide layer is formed on the well. 
     
     
       19. The semiconductor device according to  claim 9 , wherein said at least one dummy element region comprises a well, an impurity diffusion layer for a well contact is formed in a surface region of the well, and the metal silicide layer is formed on the well and the impurity diffusion layer. 
     
     
       20. The semiconductor device according to  claim 9 , wherein said at least one dummy element region includes a dummy gate electrode. 
     
     
       21. The semiconductor device according to  claim 9 , wherein the metal silicide layer contains either one of Ni and Pt. 
     
     
       22. The semiconductor device according to  claim 9 , wherein the element- isolating region comprises a trench formed in the semiconductor substrate, and insulating film is buried within the trench.   
     
     
       23. The semiconductor device according to  claim 9 , comprising:
   said square region being approximately centered on the real element region and including at least a portion of said at least one dummy region.     
     
     
       24. The semiconductor device according to  claim 23 , comprising:
   said at least one dummy region surrounding said real element region.     
     
     
       25. The semiconductor device according to  claim 9 , comprising:
   said at least one dummy region surrounding said real element region.     
     
     
       26. The semiconductor device according to  claim 9 , wherein each of said real element region and said at least one dummy region comprises the same area. 
     
     
       27. The semiconductor device according to  claim 9 , comprising:
   said ratio being approximately  25   %.   
     
     
       28. A semiconductor device, comprising:
   a semiconductor substrate;        an element - isolating region formed in the semiconductor substrate;        an element region formed in the semiconductor substrate, isolated by the element - isolating region, and having a metal silicide layer with a first area; and        at least one dummy region formed in the semiconductor substrate, and having a metal silicide layer with a second area,        wherein a ratio of a sum of the first and second areas occupied in said in a  1  μm square region containing the element region and at least a portion of said at least one dummy region, is at least  25   %.   
     
     
       29. The semiconductor device according to  claim 28 , comprising:
   a plurality of dummy element regions, wherein portions of a plurality of said dummy regions are included in said square region.     
     
     
       30. The semiconductor device according to  claim 28 , comprising:
   at least one of said dummy regions having a shape different than a shape of said real element region.     
     
     
       31. The semiconductor device according to  claim 28 , comprising:
   an area of at least one of said dummy regions being larger than an area of said real element region.     
     
     
       32. The semiconductor device according to  claim 28 , comprising:
   at least one of said dummy regions having a shape different than a shape of said real element region.     
     
     
       33. The semiconductor device according to  claim 28 , comprising:
   an area of at least one of said dummy regions being larger than an area of said real element region.     
     
     
       34. The semiconductor device according to  claim 28 , comprising:
   said square region being approximately centered on the real element region and including at least a portion of said at least one dummy region.     
     
     
       35. The semiconductor device according to  claim 28 , comprising:
   said dummy region surrounding said real element region.     
     
     
       36. The semiconductor device according to  claim 28 , wherein each of said real element region and said at least one dummy region comprises the same area. 
     
     
       37. A semiconductor device having a semiconductor substrate, an element- isolating region formed in the semiconductor substrate, a plurality of element regions formed in the semiconductor substrate, isolated by the element - isolating region and having a metal silicide layer, including a real element region and at least one dummy element region, formed by a method comprising:      forming said real element region and at least a portion of said dummy element region in a  1  μm square region where a ratio of a sum of an area of the real element region and an area of said at least one dummy element region occupied in said square region is  25   %  or more.     
     
     
       38. The semiconductor device according to  claim 37 , wherein said device is formed by said method comprising:
   forming a trench;        filling said trench with an insulating layer;        forming a first diffusion region in said real element region;        forming a second diffusion region in said at least one dummy element region;        forming a Ni layer over said first and second diffusion regions and said insulating layer; and        forming a silicide layer on said first and second diffusion regions.     
     
     
       39. A semiconductor, comprising:
   a semiconductor substrate;        an element - isolating region formed in the semiconductor substrate;        a real element region formed in the semiconductor substrate, isolated by the element - isolating region and having a metal silicide layer; and        means for decreasing an area occupied by said element - isolating region in a  1  micron square region containing said real element region if an area of said real element region is less than  25   %  of an area of said square region.     
     
     
       40. The semiconductor device according to  claim 39 , wherein said means comprises at least one dummy element region, wherein at least a portion of said at least one dummy element region is included in said square region. 
     
     
       41. The semiconductor device according to  claim 40 , wherein said at least one dummy element region has a shape different than a shape of said real element region. 
     
     
       42. The semiconductor device according to  claim 40 , comprising:
   an area of said at least one dummy element region being larger than an area of said real element region.     
     
     
       43. The semiconductor device according to  claim 40 , wherein each of said real element region and said means comprises the same area. 
     
     
       44. The semiconductor device according to  claim 40 , wherein the metal silicide layer contains either one of Ni and Pt. 
     
     
       45. The semiconductor device according to  claim 40 , wherein the real element region includes a diffusion region on which the metal silicide layer is formed. 
     
     
       46. The semiconductor device according to  claim 40 , wherein said device is formed by said method comprising:
   forming a trench;        filling said trench with an insulating layer;        forming a first diffusion region in said real element region;        forming a second diffusion region in said at least one dummy element region;        forming a Ni layer over said first and second diffusion regions and said insulating layer; and        forming a silicide layer on said first and second diffusion regions.     
     
     
       47. The semiconductor device according to  claim 39 , comprising:
   said means having a shape different than a shape of said real element region.     
     
     
       48. The semiconductor device according to  claim 39 , comprising said means occupying an area larger than an area of said real element region. 
     
     
       49. The semiconductor device according to  claim 39 , comprising:
   said square region being approximately centered on the real element region.     
     
     
       50. The semiconductor device according to  claim 39 , comprising:
   said means surrounding said real element region.