RF chipset architecture

Abstract

A set of radio frequency (RF) integrated circuits includes a transmit chip having a power amplifier and a receive chip adapted to work with the transmit chip. The receive chip has one or more low noise amplifiers to receive RF signals, and a processor coupled to the low noise amplifiers, the processor transmitting data through the transmit chip and receiving data from the on-chip low noise amplifiers.

1. A radio frequency transceiver system, comprising:
 a transmit chip; and 
 a receive chip adapted to be coupled to the  a transmit chip, the receive chip having a transistor device comprising: 
 a layer of gate oxide on a surface of the  a semiconductor substrate;  
 a gate electrode formed on the surface of the gate oxide, the gate electrode having a drain side;  
 a p-well implanted within a  the semiconductor substrate under the gate electrode;  
 an n-well implanted in the p-well on the drain side;  
 an n+ source region in the p-well outside of the n-well; and  
 an n+ drain region within the substrate inside the n-well.  
 
 
     
     
       2. The system of  claim 1 , wherein the n-well extends slightly  under at least a portion of the gate electrode. 
     
     
       3. The system of  claim 1 , further comprising digital  analog circuitry positioned adjacent to the transistor device. 
     
     
       4. The system of  claim 1 , wherein the p-well is deeper than the n-well. 
     
     
       5. The system of  claim 1 , further comprising a second transistor device, comprising:
 a second gate electrode formed on the surface of the gate oxide;  
 a second n-well implanted within a  the semiconductor substrate under the second gate electrode;  
 a p+ source region in the second n-well; and  
 a p+ drain region within the semiconductor substrate inside the second n-well.  
 
     
     
       6. The system of  claim 5 , wherein the second n-well is adjacent to the p-well. 
     
     
       7. The system of claim  1    5 , wherein the first and  second n-wells are formed at the same time  is adjacent to the p- well . 
     
     
       8. The system of  claim 1 , wherein the device is configured to be used in a digital circuit adjacent to a CMOS imaging element. 
     
     
       9. The system of  claim 1 , wherein the device is configured to be used in a digital circuit adjacent to a data converter. 
     
     
       10. The system of  claim 1 , wherein the device is configured to be used in a digital circuit adjacent to a radio frequency circuit. 
     
     
       11. A set of radio frequency (RF) integrated circuits, including:
 a transmit chipcomprising a power amplifier ; and  
 a receive chip adapted  configured to be coupled to the transmit chip, comprising: 
 one or more low noise amplifiers to receive RF signals, ; and  
 a processor coupled to the one or more low noise amplifiers, the processor configured to transmitting  transmit data through the transmit chip and receiving receive data from the one or more on-chip low noise amplifiers.  
 
 
     
     
       12. The set of  claim 11 , wherein the receive chip further comprises a digitally programmable filter coupled to each low noise amplifier. 
     
     
       13. The set of  claim 11 , further comprising a mixer coupled to each low noise amplifier. 
     
     
       14. The set of  claim 11 , further comprising a programmable local oscillator coupled to the processor. 
     
     
       15. The set of  claim 11 , further comprising:
 a PHY coupled to the processor; and  
 a MAC coupled to the PHY.  
 
     
     
       16. The set of  claim 11 , wherein the transmit chip further comprises a programmable gain adjustment (PGA) circuit coupled to the processor on the receive chip . 
     
     
       17. A system comprising:
   an integrated circuit having an analog portion and a digital portion integrated on a substrate, the analog portion including:      a cellular radio core; and        a short - range wireless transceiver core coupled to the cellular radio core;          wherein the digital portion includes:      a reconfigurable processor core coupled to the cellular radio core and the short - range wireless transceiver core, wherein the reconfigurable processor core is configured to control the cellular radio core and the short - range wireless transceiver core; and        wherein at least the digital portion includes a device having a gate electrode formed on the substrate, and wherein the gate electrode has a drain side, a p - well implanted within the substrate under the gate electrode, an n - well implanted in the p - well on the drain side, an n+ source region in the p - well outside of the n - well, and an n+ drain region in the n - well.       
     
     
       18. The system of  17 , wherein the integrated circuit further comprises a radio frequency ( RF )  sniffer.   
     
     
       19. The system of  claim 17 , wherein the digital portion further comprises a memory comprising a volatile portion and a non- volatile portion.   
     
     
       20. The system of  claim 17 , wherein the reconfigurable processor core comprises a read only memory ( ROM )  having stored thereon code executable by the reconfigurable processor core to implement multiple wireless protocols usable to control the cellular radio core and the short - range wireless transceiver core.