Image data processing system

Abstract

The present invention provides an image data processing system to increase the speed of on-screen display (OSD) image processing. The image data processing system comprises M color code registers for storing a plurality of color codes and a first multiplexer electrically connected to every output port of the M color code registers. The first multiplexer comprises a control port for inputting an N-bit image code, and the first multiplexer chooses one of the outputs of the M color code registers as its output according to the N-bit image code. The image data processing system comprises a processor for storing M color codes in the M color code registers and periodically transmitting a plurality of N-bit image codes to the control port of the first multiplexer so that the first multiplexer periodically chooses one of the color codes stored in the M color code registers as its output according to one of the N-bit image codes.

1. An image data processing system comprising:
 2N 2   N  color code registers for storing a plurality of color codes;  
 a first multiplexer electrically connected to every output port of the 2N   2   N  color code registers, the first multiplexer comprising a control port for inputting an N-bit image code, the first multiplexer choosing one of the outputs of the M color code registers as output according to the N-bit image code;  
 a processor for storing 2N   2   N  color codes in the 2N   2   N  color code registers, and periodically transmitting a plurality of N-bit image codes to the control port of the first multiplexer so that the first multiplexer periodically chooses one of the color codes stored in the 2N   2   N  color code registers as output according to one of the N-bit image codes:  
 an image memory electrically connected to an output port of the first multiplexer for storing a plurality of color codes received from the first multiplexer;  
 an address controller electrically connected to both the processor and the image memory for storing the plurality of color codes received from the first multiplexer into a predetermined address of the image memory according to a command from the processor;  
 a display connected to an output port of the image memory; and  
 a display controller electrically connected to both the display and the address controller for transmitting the plurality of color codes stored in the image memory to the display via the address controller, and for controlling operations of the display so that the display is able to show a first image according to the plurality of color codes.  
 
     
     
       2. The image data processing system of  claim 1  wherein N is equal to 1, the image data processing system further comprising a shift register electrically connected to both the first multiplexer and the processor for storing a plurality of one-byte image codes received from the processor, and the shift register periodically transmitting the plurality of image codes to the control port of the first multiplexer so that the first multiplexer periodically chooses one of the color codes stored in the two color code registers as output according to one of the image codes. 
     
     
       3. The image data processing system of  claim 1  wherein N is greater than 1, the image data processing system further comprising a first-in-first-out register electrically connected to both the first multiplexer and the processor for storing a plurality of N-bit image codes received from the processor, and the first-in-first-out register periodically transmitting the plurality of image codes to the control port of the first multiplexer so that the first multiplexer periodically transforms the plurality of image codes into a corresponding plurality of color codes. 
     
     
       4. The image data processing system of  claim 1  wherein the display is a liquid crystal display (LCD). 
     
     
       5. The image data processing system of  claim 1  further comprising a second multiplexer, wherein the second multiplexer comprises two input ports and an output port, the two input ports of the second multiplexer being electrically connected to the output port of the image memory and an external image input port, respectively, and the output port of the second multiplexer being electrically connected to the input port of the display, the external image input port being used to input external image data so that the display is able to show a second image, and the display controller controls displaying of the first image and the second image via the second multiplexer so that both the first image and the second image overlap when shown on the display. 
     
     
       6. The image data processing system of  claim 1  further comprising a third multiplexer and a mode controller, wherein the third multiplexer comprises two input ports, an output port, and a control port, the two input ports of the third multiplexer electrically connected to the output port of the first multiplexer and an output part of a predetermined color code register from the plurality of color code registers, respectively, and the output port and control port of the third multiplexer being electrically connected to the input port of the image memory and the output port of the mode controller, respectively, the processor being able to store a color code in the predetermined color code register and a mode code in the mode controller, the third multiplexer choosing the output of the predetermined color code register according to the mode code so that the color code stored in the predetermined color cods  code register is stored into a predetermined address of the image memory. 
     
     
       7. The image data processing system of  claim 6  wherein the third multiplexer further comprises a third input port electrically connected to the processor, and the processor is able to store the plurality of color codes into the predetermined address of the image memory via the third input port of the third multiplexer. 
     
     
       8. An image data processing system comprising:
 an image memory for storing a color code, an output port of the image memory being electrically connected to a display;  
 a processor for storing the color code in the image memory;  
 an address controller electrically connected to both the processor and the image memory for storing the color code in a plurality of addresses of the image memory according to the address information of an image area received from the processor, and the plurality of addresses of the image memory storing the color code corresponding to at least two pixels of the image area;  
 a display controller electrically connected to both the display and the address controller for transmitting the color code stored in the image memory to the display via the address controller, and controlling the operations of the display so that the display shows a first image according to the color code; and  
 a second  multiplexer comprising: 
 two input ports electrically connected to the output port of the image memory and an external image input port, respectively, the external image input port being used to input external image data so that the display is able to show a second image; and  
 an output port electrically connected to the input port of the display, the display controller controlling the exhibitions of the first image and the second image via the second  multiplexer so that both the first image and the second image overlap when shown on the display.  
 
 
     
     
       9. The image data processing system of  claim 8  wherein the display is a liquid crystal display. 
     
     
       10. An image data processing system comprising:
 2N 2   N  color code registers for storing a plurality of color codes;  
 a first multiplexer electrically connected to every output port of the 2N   2   N  color code registers, the first multiplexer comprising a control port for inputting an N-bit image code, the first multiplexer choosing one of the outputs of the 2N   2   N  color code registers as output according to the N-bit image code;  
 a processor for storing 2N   2   N  color codes in the 2N   2   N  color code registers, and periodically transmitting a plurality of N-bit image codes to the control port of the first multiplexer so that the first multiplexer periodically chooses one of the color codes stored in the 2N   2   N  color code registers as output according to one of to N-bit image codes;  
 an image memory electrically connected to an output port of the first multiplexer for storing a plurality of color code received from the first multiplexer;  
 an address controller electrically connected to both the processor and the image memory for storing the plurality of color codes received from the first multiplexer into a predetermined address of the image memory according to a command from the processor; and  
 a mode controller for storing a mode code from the processor; and a third multiplexer comprising two input ports, an output port, and a control port, the two input ports of the third multiplexer electrically connected to the output port of the first multiplexer and an output port of a predetermined color code register from the plurality of color code registers, respectively, and the output port and control port of the third multiplexer being electrically connected to the input port of the image memory and the output port of the mode controller, respectively the processor being able to store a color code in the predetermined color code register, the third multiplexer choosing the output of the predetermined color code register according to the mode code so that the color code stored in the predetermined color code register is stored into a predetermined address of the image memory.  
 
     
     
       11. The image data processing system of  claim 10  wherein N is equal to 1, the image data processing system further comprising a shift register electrically connected to both the first multiplexer and the processor for storing a plurality of one-byte image codes received from the processor, and the shift register periodically transmitting the plurality of image codes to the control port of the first multiplexer so that the first multiplexer periodically chooses one of the color codes stored in the two color code registers as output according to one of the image codes. 
     
     
       12. The image data processing system of  claim 10  wherein N is greater than 1, the image data processing system further comprising a first-in-first-out register electrically connected to both the first multiplexer and the processor for storing a plurality of N-bit image codes received from the processor, and the first-in-first-out register periodically transmitting the plurality of image codes to the control port of the first multiplexer so that the first multiplexer periodically transforms the plurality of image codes into a corresponding plurality of color codes. 
     
     
       13. The image data processing system of  claim 10  wherein the output port of the image memory is electrically connected to a display, the image data processing system further comprising a display controller electrically connected to both the display and the address controller for transmitting the plurality of color codes stored in the image memory to the display via the address controller, and for controlling operations of the display so that the display is able to show a first image according the plurality of color codes. 
     
     
       14. The image data processing system of  claim 13  wherein the display is a liquid crystal display (LCD). 
     
     
       15. The image data processing system of  claim 13  further comprising a second multiplexer, wherein the second multiplexer comprises two input ports and an output port, the two input ports of the second multiplexer being electrically connected to the output port of the image memory and an external image input port, respectively, and the output port of the second multiplexer being electrically connected to the input port of the display, the external image input port being used to input external image data so that the display is able to show a second image, and the display controller controls displaying of the first image and the second image via the second multiplexer so that both the first image and the second image overlap when shown on the display. 
     
     
       16. The image data processing system of  claim 10  wherein the third multiplexer further comprises a third input port electrically connected to the processor, and the processor is able to store the plurality of color codes into the predetermined address of the image memory via the third input port of the third multiplexer. 
     
     
       17. An image data processing system, comprising:
   an image memory configured to store a color code, wherein the image memory includes an output port coupled to a multiplexer, and wherein the image memory is further configured to be coupled to a display via the multiplexer;        a processor configured to direct storage of the color code in the image memory;        an address controller configured to control storage of the color code at a plurality of addresses in the image memory;        a display controller coupled to the address controller and configured to be coupled to the display to allow the color code stored in the image memory to be transmitted to the display, so that the display shows a first image according to the stored color code; and        the multiplexer including:      a plurality of input ports coupled to the output port of the image memory and an external image input port, respectively, wherein the external image input port is configured to provide external image data so that the display shows a second image; and        an output port configured to be operably coupled to an input port of the display, wherein the display controller is further configured to control both the first image and the second image via the multiplexer so that both the first image and the second image overlap on the display.       
     
     
       18. The image data processing system of  claim 17 , wherein the address controller is further configured to control storage of the color code at a plurality of addresses in the image memory according to the address information of an image area, and wherein the plurality of addresses in the image memory correspond to at least two pixels of the image area. 
     
     
       19. The image data processing system of  claim 17 , wherein the display comprises a liquid crystal display ( LCD ). 
     
     
       20. A method, comprising:
   selecting a drawing mode for a display;        providing an image code to a multiplexer such that the multiplexer chooses one or more color codes stored in one or more color code registers;        selecting the one or more color codes based, at least in part, on the selected drawing mode;        providing the selected one or more color codes to a display controller;        outputting image data based, at least in part, on the provided one or more color codes; and        storing the selected one or more color codes in an image memory using an address controller.     
     
     
       21. The method of  claim 20 , wherein the drawing mode comprises one of a single- bit map mode, a  16   - bit map mode, or a block mode.   
     
     
       22. The method of  claim 20 , wherein said outputting image data further comprises:
   retrieving the selected one or more color codes from a predetermined address in the image memory.     
     
     
       23. The method of  claim 20 , wherein the multiplexer is a first multiplexer, and wherein said outputting image data further comprises:
   providing the image data to a second multiplexer such that the second multiplexer chooses from image data stored in the image memory or from external image data; and        selecting image data to be output to the display controller.