Pinned photodiode photodetector with common pixel transistors and binning capability

Abstract

A lock in pinned photodiode photodetector includes a plurality of output ports which are sequentially enabled. Each time when the output port is enabled is considered to be a different bin of time. A specified pattern is sent, and the output bins are investigated to look for that pattern. The time when the pattern is received indicates the time of flight.A CMOS active pixel image sensor includes a plurality of pinned photodiode photodetectors that use a common output transistor. In one configuration, the charge from two or more pinned photodiodes may be binned together and applied to the gate of an output transistor.

1. A method, comprising:
 accumulating photocarriers in each of a plurality of photocarrier integrators and successively enabling each of said plurality of photocarrier integrators to connect to a common photodiode, each of said photocarrier integrators connecting to said common photodiode through a respective photodiode output port, said plurality of photocarrier integrators accumulating photocarriers generated by said photodiode during different time periods from one another.    
     
     
       2. A method as in  claim 1 , wherein said enabling comprises actuating a gate that is connected between each said photocarrier integrator and said photodiode. 
     
     
       3. A method as in  claim 2 , further comprising, after said enabling, detecting a number of carriers accumulated in said photodiode during at least two of said time periods by detecting the number of photocarriers accumulated in at least two said photocarrier integrators. 
     
     
       4. A method as an  claim 2 , wherein said photodiode is a pinned photodiode, and further comprising, after said enabling, detecting a number of carriers accumulated in said pinned photodiode during at least two of said time periods by decting the number of photocarriers accumulated in at least two said photocarrier integrators. 
     
     
       5. A method as in  claim 1 , wherein there are four of said photocarrier integrators, and said successively enabling comprises using a first photocarrier integrator to accumulate photocarrier between times 0 and π/2, a second photocarrier integrator to accumulate photocarriers between times π/2 and π; a third photocarrier integrator to accumulate photocarriers between times π and 3π/2, and a fourth photocarrier integrator to accumulate photocarriers between times 3π/2 and 2π. 
     
     
       6. A method as in  claim 1 , further comprising detecting a phase shift of light received by said photodiode by detecting accumulated charge in at least two photocarrier integrators. 
     
     
       7. A method, comprising:
 generating photocarriers in a photodiode within a pixel during a plurality of time periods;    accumulating photocarriers in each of a plurality of photocarrier integrators within said pixel such that each photocarrier integrator accumulates photocarriers generated during a time period different from a time period in which other photocarrier integrators accumulate photocarriers; and    sampling said photocarriers from said photocarrier integrators;    determining a range of an object using said sampled photocarriers.    
     
     
       8. A method as in  claim 7 , further comprising controlling each of said photocarrier integrators to be connected to said photodiode during said different time period. 
     
     
       9. A method as in  claim 8 , wherein said controlling comprises enabling a gate, said gate being connected to said photodiode and to one of said photocarrier integrators. 
     
     
       10. A method as in  claim 9 , wherein there are four of said photocarrier integrators, and wherein said enabling comprises successively enabling a first photocarrier integrator to accumulate photocarriers between times 0 and π/2, a second photocarrier integrator to accumulate photocarriers between times π/2 and π; a third photocarrier integrator to accumulate photocarriers between times π and 3π/2, and a fourth photocarrier integrator to accumulate photocarriers between times 3π/2 and 2π. 
     
     
       11. A method as in  claim 7 , wherein there are four of said photocarriers integrators, and said sampling comprises sampling photo carriers which are 90 degrees out of phase with one another. 
     
     
       12. A method, comprising:
 sampling a plurality of different samples of light in a photodiode, each of said plurality of different samples being 90 degrees out of phase with one another; and    successively gating photocarriers representing each of said different samples from said photodiode through a respective output port, each output port associated with a respective photocarrier integrator, such that each photocarrier integrator accumulates a different sample than other of said photocarrier integrators.    
     
     
       13. A method as in  claim 12 , further comprising detecting a phase shift using said samples of light. 
     
     
       14. A method as in  claim 12 , wherein there are four different gates connected to said photodiode each gating a different sample. 
     
     
       15. A method as in  claim 12 , wherein there are four photocarrier integrators, and wherein said act of gating comprises successively enabling a first photocarrier integrator to accumulate photocarriers between times 0 and π/2, a second photocarrier integrator to accumulate photocarriers between times π/2 and π; a third photocarrier integrator to accumulate photocarriers between times π and 3π/2, and a fourth photocarrier integrator to accumulate photocarriers between times 3π/2 and 2π. 
     
     
       16. A method of operating a range finding sensor, the method comprising;
 providing a plurality of photodiodes, each photodiode having a first output port for switchably coupling each respective photodiode to a first photocarrier integrator in a same pixel as said photodiode and a second output port for switchably coupling each photodiode to a second photocarrier integrator in a same pixel as said photodiode;    generating first photocarriers in said photodiodes in response to light received during a first time period;    transferring said first photocarriers to respective first photocarrier integrators via said first output ports;    generating second photocarriers in said photodiodes in response to light received during a second time period; and    transferring said second photocarriers to respective second photocarrier integrators via said second output ports.    
     
     
       17. The method of  claim 16 , further comprising outputting said first photocarriers from first photocarrier integrators and outputting said second photocarriers from second photocarrier integrators. 
     
     
       18. The method of  claim 17 , wherein the act of outputting said first photocarriers comprises summing outputs of all of said first photocarrier integrators, and wherein the act of outputting said second photocarriers comprises summing outputs of all of said second photocarrier integrators. 
     
     
       19. The method of  claim 16 , further comprising counting the amount of photocarriers in said first photocarriers integrator and counting the amount of said second photocarriers in said second photocarrier integrator. 
     
     
       20. The method of  claim 19 , further comprising determining a range of an object using the results of said acts of counting. 
     
     
       21. The method of  claim 16 , wherein said act of providing a plurality of photodiodes includes providing said plurality of photodiodes within a common pixel. 
     
     
       22. The method of  claim 16 , wherein said act of transferring said first photocarriers comprises transferring said first photocarriers to respective first output drains by operating first gates connected to said photodiodes and said first output drains, and wherein said act of transferring said second photocarriers comprises transferring said second photocarriers to respective second output drains by operating second gates connected to said photodiodes and said second output drains. 
     
     
       23. The method of  claim 16 , wherein each photodiode further has a third output port for switchably coupling each photodiode to a third photocarrier integrator in a same pixel as said photodiode and a fourth output port for switchably coupling each photodiode to a fourth photocarrier integrator in a same pixel as said photodiode, and further comprising:
 generating third photocarriers in said photodiodes in response to light received during a third time period;    transferring said third photocarriers to respective third photocarrier integrators via said third output ports;    generating fourth photocarriers in said photodiodes in response to light received during a fourth time period; and    transferring said fourth photocarriers to respective fourth photocarrier integrators via said fourth output ports.    
     
     
       24. The method of  claim 23 , further comprising outputting said first photocarriers from said first photocarrier integrators, outputting said second photocarriers from said second photocarrier integrators, outputting said third photocarriers from said third photocarrier integrators, and outputting said fourth photocarriers from said fourth photocarrier integrators. 
     
     
       25. The method of  claim 24 , wherein the act of outputting said first photocarriers comprises summing outputs of all of said first photocarrier integrators, wherein the act of outputting said second photocarriers comprises summing outputs of all of said second photocarrier integrators, wherein the act of outputting said third photocarriers comprises summing outputs of all of said third photocarrier integrators, and wherein the act of outputting said fourth photocarriers comprises summing outputs of all of said fourth photocarrier integrators. 
     
     
       26. A method comprising:
   providing an array of pixels of a CMOS active pixel image sensor, the array comprising a plurality of rows of pinned photodiodes and a plurality of columns of pinned photodiodes, and including first, second, third, and fourth pinned photodiodes in first, second, third, and fourth different rows, respectively, of the plurality of rows;        providing an in - pixel buffer transistor comprising a gate and coupled between a supply voltage and an output node, wherein the buffer transistor is configured to control a transfer of charge between the supply voltage and the output node in accordance with a voltage applied to the gate;        providing a first transfer transistor coupled between the first pinned photodiode and the gate, wherein the first transfer transistor is configured to control a transfer of charge between the first pinned photodiode and the gate;        providing a second transfer transistor coupled between the second pinned photodiode and the gate, wherein the second transfer transistor is configured to control a transfer of charge between the second pinned photodiode and the gate;        providing a third transfer transistor coupled between a third pinned photodiode and the gate, wherein the third transfer transistor is configured to control a transfer of charge between the third pinned photodiode and the gate;        providing a fourth transfer transistor coupled between a fourth pinned photodiode and the gate, wherein the fourth transfer transistor is configured to control a transfer of charge between the fourth pinned photodiode and the gate; and        providing a reset transistor coupled to the gate, wherein when the reset transistor is enabled, charge is transferred to the gate.     
     
     
       27. The method of  claim 26 , further comprising enabling the first transfer transistor and the second transfer transistor during a same period of time to bin charge from both the first pinned photodiode and the second pinned photodiode on the gate. 
     
     
       28. The method of  claim 26 , further comprising enabling the first, second, third, and fourth transfer transistors during a same period of time to bin charge from the first, second, third and fourth pinned photodiodes on the gate. 
     
     
       29. The method of  claim 26 , further comprising providing an in- pixel selection transistor.   
     
     
       30. The method of  claim 26 , wherein the reset transistor is coupled between the gate and the supply voltage. 
     
     
       31. The method of  claim 26 , further comprising:
   providing a first charge collection region in a semiconductor material adjacent to the first and second pinned photodiodes, wherein the first transfer transistor is configured to control a transfer of charge between the first pinned photodiode and the first charge collection region and the second transfer transistor is configured to control a transfer of charge between the second pinned photodiode and the first charge collection region;        providing a second charge collection region in the semiconductor material adjacent to the third and fourth pinned photodiodes, wherein the third transfer transistor is configured to control a transfer of charge between the third pinned photodiode and the second charge collection region and the fourth transfer transistor is configured to control a transfer of charge between the fourth pinned photodiode and the second charge collection region; and        providing an electrical interconnect above the semiconductor material to couple the first region and the second region to the gate.     
     
     
       32. The method of  claim 26 , wherein the first, second, third, and fourth pinned photodiodes are in a same column of the plurality of columns of pinned photodiodes. 
     
     
       33. A method comprising:
   accumulating charge in a first pinned photodiode of a first pixel that occupies a first row of an array of pixels of a CMOS active pixel imager comprising in - pixel buffer transistors;        transferring charge from the first pinned photodiode directly to a first diffusion region via a first transistor;        accumulating charge in a second pinned photodiode of a second pixel that occupies a second row, below the first row, of the array;        transferring charge from the second pinned photodiode directly to the first diffusion region via a second transistor;        accumulating charge in a third pinned photodiode of a third pixel that occupies a third row, below the second row, of the array;        transferring charge from the third pinned photodiode directly to a second diffusion region, separate from the first diffusion region, via a third transistor;        accumulating charge in a fourth pinned photodiode of a fourth pixel that occupies a fourth row, below the third row, of the array;        transferring charge from the fourth pinned photodiode directly to the second diffusion region via a fourth transistor;        applying charge from the first diffusion region to a gate of a fifth transistor coupled between a supply voltage and an output; and        applying charge from the second diffusion region to the gate of the fifth transistor, wherein the fifth transistor is common to the first, second, third, and fourth pixels.     
     
     
       34. The method of  claim 33 , further comprising turning on the first transistor and the second transistor during a same period of time. 
     
     
       35. The method of  claim 34 , further comprising turning on the third transistor and the fourth transistor during a same period of time. 
     
     
       36. The method of  claim 33 , further comprising resetting the first and second diffusion regions via a single reset transistor. 
     
     
       37. The method of  claim 36 , wherein the CMOS active pixel image sensor further comprises in- pixel selection transistors.   
     
     
       38. The method of  claim 33 , wherein the CMOS active pixel image sensor further comprises in- pixel selection transistors.   
     
     
       39. The method of  claim 33 , wherein the first, second, third, and fourth pixels occupy a single column of the array. 
     
     
       40. A method comprising:
   enabling a CMOS active pixel image sensor to be exposed to light, wherein first, second, third, and fourth pinned photodiodes disposed in first, second, third, and fourth adjacent rows of photodiodes, respectively, of the CMOS active pixel image sensor are configured to generate first, second, third, and fourth charges upon exposure to the light, respectively;        enabling the first charge to be transferred to a gate of an output transistor via a first transfer transistor between the first pinned photodiode and the gate;        enabling the second charge to be transferred to the gate via a second transfer transistor between the second pinned photodiode and the gate;        enabling the third charge to be transferred to the gate via a third transfer transistor between the third pinned photodiode and the gate; and        enabling the fourth charge to be transferred to the gate via a fourth transfer transistor between the fourth pinned photodiode and the gate.     
     
     
       41. The method of  claim 40 , wherein the enabling the first charge to be transferred and the enabling the second charge to be transferred occur during a same period of time. 
     
     
       42. The method of  claim 40 , wherein the enabling the first charge to be transferred, the enabling the second charge to be transferred, the enabling the third charge to be transferred, and the enabling the fourth charge to be transferred occur during a same period of time. 
     
     
       43. The method of  claim 40 , further comprising enabling the gate to be reset via a reset transistor. 
     
     
       44. The method of  claim 40 , further comprising enabling pixels of the CMOS active pixel image sensor to be buffered using in- pixel buffer transistors.   
     
     
       45. The method of  claim 44 , further comprising enabling pixels of the CMOS active pixel image sensor to be selected for readout using in- pixel selection transistors.   
     
     
       46. The method of  claim 44 , wherein the first and second transfer transistors share a common first source/drain region adjacent to gates of the first and second transfer transistors, the third and fourth transfer transistors share a common second source/drain region adjacent to gates of the third and fourth transfer transistors, and the common first source/drain region is coupled to the common second source/drain region via an electrical interconnect disposed above the first and second source/drain regions. 
     
     
       47. The method of  claim 40 , wherein the first, second, third, and fourth pinned photodiodes are disposed in a first column of photodiodes. 
     
     
       48. A method comprising:
   providing a device containing a CMOS active pixel image sensor, the sensor comprising an array of pixels and a plurality of pinned photodiodes arranged in rows including at least first, second, third, and fourth separate rows of photodiodes, each pixel including at least one pinned photodiode, the device configured to expose the CMOS active pixel image sensor to light, in response to which each pinned photodiode of the plurality of pinned photodiodes is to generate charge;        providing a first circuit configured to operate a gate of a first n - channel transfer transistor coupled between a first pinned photodiode of the first row of the plurality of pinned photodiodes and a gate of an n - channel in - pixel buffer transistor, wherein the buffer transistor is coupled between a supply voltage and an output;        providing a second circuit configured to operate a gate of a second n - channel transfer transistor coupled between a second pinned photodiode of the second row of the plurality of pinned photodiodes and the gate of the buffer transistor;        providing a third circuit configured to operate a gate of a third n - channel transfer transistor coupled between a third pinned photodiode of the third row of the plurality of pinned photodiodes and the gate of the buffer transistor;        providing a fourth circuit configured to operate a gate of a fourth n - channel transfer transistor coupled between a fourth pinned photodiode of the fourth row of the plurality of pinned photodiodes and the gate of the buffer transistor; and        providing a fifth circuit configured to operate a gate of an n - channel reset transistor coupled to the gate of the buffer transistor to reset a voltage on the gate of the buffer transistor.     
     
     
       49. The method of  claim 48 , wherein the first circuit and the second circuit are configured to operate the first transfer transistor and the second transfer transistor, respectively, in a manner that causes charge from the first pinned photodiode and the second pinned photodiode to be binned together on the gate of the buffer transistor. 
     
     
       50. The method of  claim 48 , wherein the first, second, third, and fourth circuits are configured to operate the first, second, third, and fourth transfer transistors, respectively, in a manner that causes charge from the first, second, third, and fourth pinned photodiodes to be binned together on the gate of the buffer transistor. 
     
     
       51. The method of  claim 48 , further comprising providing a plurality of in- pixel selection transistors.   
     
     
       52. The method of  claim 48 , wherein each pixel includes at least one buffer transistor. 
     
     
       53. The method of  claim 48 , wherein the reset transistor is coupled between the gate of the buffer transistor and the supply voltage. 
     
     
       54. The method of  claim 48 , further comprising:
   providing a first charge collection region in a semiconductor material adjacent to the first and second pinned photodiodes, wherein the first transfer transistor is configured to control a transfer of charge between the first pinned photodiode and the first charge collection region and the second transfer transistor is configured to control a transfer of charge between the second pinned photodiode and the first charge collection region; and        providing a second charge collection region, separate from the first region, in the semiconductor material adjacent to the third and fourth pinned photodiodes, wherein the third transfer transistor is configured to control a transfer of charge between the third pinned photodiode and the second charge collection region and the fourth transfer transistor is configured to control a transfer of charge between the fourth pinned photodiode and the second charge collection region.     
     
     
       55. The method of  claim 54 , wherein the first charge collection region is a drain of both the first and second transfer transistors, and the second charge collection region is a drain of both the third and fourth transfer transistors. 
     
     
       56. The method of  claim 55 , further comprising providing an electrical interconnect above the semiconductor material to couple the first region and the second region to the gate. 
     
     
       57. The method of  claim 48 , wherein the first, second, third, and fourth pinned photodiodes are arranged in a single column of the plurality of pinned photodiodes. 
     
     
       58. A method comprising:
   exposing a CMOS active pixel imager to light;        generating signals responsive to the light in an array of pixels of the imager using photodiodes and in - pixel buffer transistors, comprising the steps of:      activating a first transfer transistor to transfer charge from a first photodiode in a first row of the array to a gate of an in - pixel buffer transistor of the image sensor;        activating a second transfer transistor to transfer charge from a second photodiode in a second row of the array to the gate;        activating a third transfer transistor to transfer charge from a third photodiode in a third row of the array to the gate; and        activating a fourth transfer transistor to transfer charge from a fourth photodiode in a fourth row of the array to the gate.       
     
     
       59. The method of  claim 58 , wherein at least two of the steps of activating occur at a same time. 
     
     
       60. The method of  claim 58 , further comprising activating a reset transistor to reset the gate. 
     
     
       61. The method of  claim 60 , further comprising activating an in- pixel selection transistor to selectively read an output from the in - pixel buffer transistor.   
     
     
       62. The method of  claim 61 , wherein the activating the first and second transfer transistors transfers charge to a common drain of the first and second transfer transistors, and the activating the third and fourth transfer transistors transfers charge to a common drain of the third and fourth transfer transistors. 
     
     
       63. The method of  claim 58 , wherein the activating the first and second transfer transistors transfers charge to a common drain of the first and second transfer transistors, and the activating the third and fourth transfer transistors transfers charge to a common drain of the third and fourth transfer transistors. 
     
     
       64. The method of  claim 63 , wherein the first, second, third, and fourth photodiodes are disposed in the same column of the array. 
     
     
       65. The method of  claim 58 , wherein the first, second, third, and fourth photodiodes are disposed in the same column of the array.