System and method for optimizing clock speed generation in a computer

Abstract

The present invention relates to a method of reducing a clock speed of a host bus to extend battery life and its operating time when a battery is supplying electric energy for a portable computer. A bus clock controlling apparatus according to the present invention includes power mode detecting means detecting a current power mode, the power mode indicative of which power source supplies the portable computer with electric energy; and clock adjusting means adjusting frequency of an applied clock from a clock generator based on the detected power mode by said power mode detecting means, and applying the frequency-adjusted clock to one or more controlling devices. Due to this invention, an electric energy stored in a battery equipped in a portable computer is saved, as a result, the battery life is extended.

1. An apparatus having a CPU wherein the improvement comprises:
 a clock generator generating a first clock signal for the CPU, and a second clock for the  a bridge controller, wherein the first and second clock signals are two distinct clock signals outputted by the clock generator and have different frequencies; and  
 athe bridge controller comprising a logic device for outputting the second clock signal adjusted based on a power source and independent of the first clock signal.  
 
     
     
       2. The apparatus of  claim 1 , wherein the bridge controller controls a clock speed of a bus connected between the CPU and the bridge controller for data communication among a plurality of peripheral devices of the apparatus using the adjusted second clock. 
     
     
       3. The apparatus of  claim 1 , wherein the power source is one of AC power mode and battery power mode. 
     
     
       4. The apparatus of  claim 1 , wherein the apparatus further includes a video processor and the clock generator generates a third clock signal for the video processor, the third clock signal being distinct from the first and second clock signals and having a different frequency than the first and second clock signals. 
     
     
       5. The apparatus of  claim 4 , wherein the improvement further comprises a second logic device for receiving the third clock signal and adjusting the third clock signal based on the power source. 
     
     
       6. The apparatus of  claim 4 , wherein the first clock signal has a higher frequency than the second clock signal and the second clock signal has a higher frequency than the third clock signal, and wherein the bridge controller controls a clock speed of a bus for data communication with the CPU. 
     
     
       7. The apparatus of  claim 1 , wherein the logic device increases a frequency of the second clock signal in an AC power mode and outputs the second clock signal without a frequency adjustment in a battery power mode. 
     
     
       8. The apparatus of  claim 1 , wherein the logic device outputs the second clock signal in a battery power mode without a frequency adjustment. 
     
     
       9. The apparatus of  claim 5 , wherein the second logic device increases a frequency of the third clock signal in an AC power mode and outputs the third clock signal without a frequency adjustment in a battery power mode. 
     
     
       10. The apparatus of  claim 5 , wherein the second logic device outputs the third clock signal in a battery power mode without a frequency adjustment. 
     
     
       11. The apparatus of  claim 5 , wherein the first logic is a phase locked loop (PLL) and the second logic device is a PLL. 
     
     
       12. An apparatus having a CPU and a bridge controller, wherein the improvement comprises:
 a clock generator generating a first clock signal; and  
 a clock adjustor receiving the first clock signal and operating in a power source mode, said clock adjustor generating a second clock signal for the CPU and a third clock signal for the bridge controller, wherein the second and third clock signals are two distinct clock signals outputted by the clock adjustor and have frequencies that are independent of each other, wherein the apparatus further includes a video processor and the clock adjustor generates a fourth clock signal for the video processor, the fourth clock signal being distinct from the second and third clock signals and having a different frequency than the second and third clock signals.  
 
     
     
       13. The apparatus of  claim 12 , wherein the bridge controller controls a clock speed of a bus for data communication among a plurality of peripheral devices of the apparatus. 
     
     
       14. The apparatus of  claim 13 , wherein the clock adjustor is a phase locked loop (PLL), and wherein the bus is a host bus. 
     
     
       15. The apparatus of  claim 12 , wherein the CPU further comprises a phase locked loop (PLL) receiving the second clock signal for the CPU and adjusting the second clock signal based on one of AC power mode and battery power mode. 
     
     
       16. The apparatus of  claim 12 , wherein the second clock signal has a higher frequency than the third clock signal and the third clock signal has a higher frequency than the fourth clock signal. 
     
     
       17. The apparatus of  claim 12 , wherein the power source is one of an AC power mode or a battery power mode. 
     
     
       18. The apparatus of  claim 12 , wherein the clock adjuster adjusts the third clock signal for the bridge controller based on the power source mode and independent of the second clock signal. 
     
     
       19. The apparatus of  claim 12 , wherein the second and third clock signals are independent of each other in each of at least two power source modes, and wherein the second clock signal includes at least two different frequencies selected in accordance with the power source mode. 
     
     
       20. A method for performing clock speed generation, comprising:
 receiving a base clock signal;  
 selectively multiplying the base clock signal by a first factor to produce a first higher frequency clock signal, and by a second factor to produce a second higher frequency clock signal, wherein the first and second higher frequency clock signals are different and phase-locked with the base clock signal;  
 receiving a power mode signal;  
 selectively outputting the first higher frequency clock signal to a first device and the second higher frequency clock signal to a second device based on the power mode signal, wherein the first device is a processor and the second device is a bridge controller; and  
 generating a third higher frequency clock signal for a video processor, wherein the third clock signal being distinct from the first and second clock signals and having a different frequency than the first and second clock signals.  
 
     
     
       21. The method of  claim 20 , wherein the power mode signal is an AC power mode signal or a battery power mode signal and the second higher frequency clock signal is selectively output independent of the first higher frequency clock signal. 
     
     
       22. The method of  claim 20 , wherein the second higher frequency clock signal is selectively output independent of the first higher frequency clock signal, and wherein the second higher frequency clock signal is selectively output by being output as is or reduced according to the power mode signal. 
     
     
       23. The method of  claim 20 , wherein the second higher frequency clock signal has at least two different frequencies selected in accordance with the power mode signal. 
     
     
       24. A method for performing clock speed generation, comprising:
 supplying a first clock signal by a first logic to generate a first higher frequency clock signal to a CPU;  
 supplying a second clock signal by a second logic to generate a second higher frequency clock signal to a bridge controller, wherein the first and second clock signals are distinct;  
 receiving by the second logic, a power mode signal and adjusting the second clock signal; and  
 selectively outputting the second higher frequency clock signal based on the power mode signal independent of the first clock signal, wherein the bridge controller controls a clock speed of a bus connected therebetween for data communication with the CPU using the outputted second higher frequency clock signal.  
 
     
     
       25. The method of  claim 24 , wherein the first clock signal is greater than the second clock signal, wherein the power mode signal is an AC power mode signal or battery power mode signal. 
     
     
       26. The method of  claim 24 , wherein the first logic and the second logic are PLLs (Phase Locked Loop). 
     
     
       27. A mobile terminal, comprising:
   a processing unit operating at a first clock and a bridge controller provided with a second clock, each configured to process data,        wherein the first and second clock signals are two distinct clock signals and have different frequencies; and        a video processing unit configured to process video data and to operate at a third clock signal,        wherein the third clock signal is distinct from the first and second clock signals and has a different frequency than at least one of the first and second clock signals, and the frequency of the third clock signal is varied based on a power source.      
     
     
       28. The mobile terminal of  claim 27 , wherein the power source is one of AC power mode and battery power mode.  
     
     
       29. The mobile terminal of  claim 27 , wherein a frequency of the first clock signal of the processing unit is varied based on the power source.  
     
     
       30. The mobile terminal of  claim 29 , wherein the power source is one of AC power mode and battery power mode.  
     
     
       31. The mobile terminal of  claim 30 , wherein the frequency of the first clock signal is varied such that the frequency of the first clock signal in the AC power mode is higher than the frequency of the first clock signal in the battery power mode, and the frequency of the third clock signal is varied such that the frequency of the third clock signal in the AC power mode is higher than the frequency of the third clock signal in the battery power mode.  
     
     
       32. The mobile terminal of  claim 29 , further comprising:
   a first phase locked loop  ( PLL )  circuit configured to vary the frequency of the first clock signal based on the power source;        a second PLL circuit configured to control the second clock signal; and        a third PLL circuit configured to vary the frequency of the third clock signal based on the power source.      
     
     
       33. The mobile terminal of clam  32 , wherein the first, second and third PPL circuits are provided in the processing unit, the bridge controller, and the video processing unit, respectively.  
     
     
       34. A mobile terminal, comprising:
   a processing unit having a first phase locked loop  ( PLL )  circuit and configured to operate at a first clock;        a bridge controller having a second PLL circuit and configured to operate at a second clock;        a video processing unit having a third PLL circuit and configured to operate at a third clock,        wherein a frequency of the first clock of the processing unit is varied based on a power source, and a frequency of the third clock of the video processing unit is varied based on the power source.      
     
     
       35. The mobile terminal of  claim 34 , wherein the power source is one of AC power mode and battery power mode.  
     
     
       36. The mobile terminal of  claim 35 , wherein the frequency of the first clock is varied such that the frequency of the first clock in the AC power mode is higher than the frequency of the first clock in the battery power mode, and the frequency of the third clock is varied such that the frequency of the third clock in the AC power mode is higher than the frequency of the third clock in the battery power mode.  
     
     
       37. The mobile terminal of  claim 36 , wherein the bridge controller controls a clock speed of a bus connected between the processing unit and the bridge controller for data communication among a plurality of peripheral devices of the mobile terminal using the second clock.  
     
     
       38. A method of controlling a mobile terminal including a processing unit, a bridge controller and a video processing unit, all operatively coupled, the method comprising:
   generating a first clock for the processing unit, a second clock for the bridge controller, and a third clock for the video processing unit, wherein the first, second and third clocks are distinct clocks and have different frequencies;        varying a frequency of the first clock based on a power mode of the mobile terminal and operating the processing unit at the varied first clock; and        varying a frequency of the third clock based on the power mode of the mobile terminal and operating the video processing unit at the varied third clock.      
     
     
       39. The method of  claim 38 , wherein the power source is one of AC power mode and battery power mode.  
     
     
       40. The method of  claim 39 , wherein the frequency of the first clock is varied such that the frequency of the first clock in the AC power mode is higher than the frequency of the first clock in the battery power mode, and the frequency of the third clock is varied such that the frequency of the third clock in the AC power mode is higher than the frequency of the third clock in the battery power mode.  
     
     
       41. The method of  claim 40 , further comprising:
   controlling, by the bridge controller, a clock speed of a bus connected between the processing unit and the bridge controller for data communication among a plurality of peripheral devices of the mobile terminal, using the second clock.      
     
     
       42. A method for performing clock speed generation, comprising:
   supplying a first clock signal by a first logic to generate a first higher frequency clock signal for a processing unit;        supplying a second clock signal for a bridge controller, wherein the first and second clock signals are distinct, and the bridge controller controls a clock speed of a bus connected therebetween for data communication with the processing unit using the second clock signal;        supplying a third clock signal by a third logic to generate a third higher frequency clock signal for a video processing unit; and        selectively outputting the third higher frequency clock signal based on a power mode signal.      
     
     
       43. The method of  claim 42 , wherein the power mode signal is an AC power mode signal or battery power mode signal.  
     
     
       44. The method of  claim 42 , wherein the first logic and the second logic are PLLs ( Phase Locked Loop ).  
     
     
       45. The method of  claim 42 , further comprising:
   selectively outputting the first higher frequency clock signal based on the power mode signal.