Dual-addressed rectifier storage device

Abstract

A read-only data storage and retrieval device is presented having no moving parts and requiring very low power. Addressing can be accomplished sequentially where the address increments automatically or can be accomplished randomly. High density storage is achieved through the use of a highly symmetric diode matrix that is addressed in both coordinate directions; its symmetry makes the Dual-addressed Rectifier Storage (DRS) Array very scaleable, particularly when made as an integrated circuit. For even greater storage flexibility, multiple digital rectifier storage arrays can be incorporated into the device, one or more of which can be made removable and interchangeable.

1. A digital logic device comprising one or more electronic information storage means, and addressing means for accessing said storage means, wherein each said electronic information storage means comprises:
 a plurality of generally parallel conductive means;   a second plurality of generally parallel conductive means that is generally perpendicular to and overlapping with the first said plurality of generally parallel conductive means;   a plurality of bits of potential information storage where a bit of said plurality of bits is present in the general vicinity of each point of intersection of each conductive means of the first said plurality of generally parallel conductive means with each conductive means of the second said plurality of generally parallel conductive means, and where the state of any said bit is determined by the presence or absence of a rectifying conductive means at each said general vicinity of said point of intersection;   means for selecting a conductive means of one plurality of generally parallel conductive means, and means for biasing the generally parallel conductive means of the other plurality of generally parallel conductive means such that each said rectifying conductive means present between a conductive means of said biased plurality of generally parallel conductive means to a conductive means of the other said plurality of generally parallel conductive means is potentially forward biased;   means for selecting a biased conductive means by electronically disabling conductive means within said biased plurality of generally parallel conductive means by shifting the voltage of those biased conductive means that are to be disabled; and   
       wherein said addressing means comprises:
 means for controlling said means for electronically selecting conductive means of one said plurality of generally parallel conductive means and for electronically selecting conductive means of the other said plurality of generally parallel conductive means. 
 
     
     
       2. The digital logic device of  claim 1 , wherein said means for selecting a conductive means of one plurality of generally parallel conductive means comprises:
 means for biasing the generally parallel conductive means of the said one plurality of generally parallel conductive means such that each said rectifying conductive means present between a conductive means of said biased plurality of generally parallel conductive means and a conductive means of the other said plurality of generally parallel conductive means is potentially forward biased; and   means for selecting a biased conductive means by electronically disabling conductive means within said biased plurality of generally parallel conductive means by shifting the voltage of those biased conductive means that are to be disabled.   
     
     
       3. The digital logic device of  claim 1 , further comprising means for detecting a conducted current through said rectifying conductive means if present at said point of intersection. 
     
     
       4. The digital logic device of  claim 1 , wherein one of said plurality of generally parallel conductive means is a plurality of generally parallel doped regions within a semiconductor material. 
     
     
       5. The digital logic device of  claim 4 , wherein the other of said plurality of generally parallel conductive means is a plurality of generally parallel metalized regions. 
     
     
       6. The digital logic device of  claim 1 , wherein said addressing means comprises means to sequentially select addressed locations. 
     
     
       7. The digital logic device of  claim 1 , wherein said addressing means comprises means to randomly select addressed locations. 
     
     
       8. The digital logic device of  claim 1 , further comprising display means for displaying alphanumeric or graphic information to its user. 
     
     
       9. The digital logic device of  claim 1 , further comprising input means to enable its user to alter its operation. 
     
     
       10. The digital logic device of  claim 1 , wherein part or all of said one more electronic storage means are removable or replaceable. 
     
     
       11. The digital logic device of  claim 1 , wherein output from the device is in a digital format. 
     
     
       12. The digital logic device of  claim 1 , wherein output from the device is in an analog format. 
     
     
       13. The digital logic device of  claim 1 , wherein output from the device is in either a digital format or an analog format. 
     
     
       14. An electronic information storage device comprising:
 a plurality of generally parallel conductive means;   a second plurality of generally parallel conductive means that is generally perpendicular to and overlapping with the first said plurality of generally parallel conductive means;   a plurality of bits of potential information storage where a bit of said plurality of bits is present in the general vicinity of each point of intersection of each conductive means of the first said plurality of generally parallel conductive means and each conductive means of the second said plurality of generally parallel conductive means, and where the state of any said bit is determined by the presence or absence of a rectifying conductive means at each said general vicinity of said point of intersection;   means for selecting a conductive means of one plurality of generally parallel conductive means, and means for biasing the generally parallel conductive means of the other plurality of generally parallel conductive means such that each said rectifying conductive means present between a conductive means of said biased plurality of generally parallel conductive means and a conductive means of the other said plurality of generally parallel conductive means is potentially forward biased; and   means for selecting a biased conductive means by electronically disabling conductive means within said biased plurality of generally parallel conductive means by shifting the voltage of those biased conductive means that are to be disabled.   
     
     
       15. The storage device of  claim 14 , wherein said means for selecting a conductive means of one plurality of generally parallel conductive means comprises:
 means for biasing the generally parallel conductive means of the said one plurality of generally parallel conductive means such that each said rectifying conductive means present between a conductive means of said biased plurality of generally parallel conductive means and a conductive means of the other said plurality of generally parallel conductive means is potentially forward biased; and   means for selecting a biased conductive means by electronically disabling conductive means within said biased plurality of generally parallel conductive means by shifting the voltage of those biased conductive means that are to be disabled.   
     
     
       16. The storage device of  claim 14 , further comprising means for detecting a conducted current through said rectifying conductive means if present at said point of intersection. 
     
     
       17. The storage device of  claim 14 , wherein one of said plurality of generally parallel conductive means is a plurality of generally parallel doped regions within a semiconductor material. 
     
     
       18. The storage device of  claim 17 , wherein said rectifying conductive means between said plurality of generally parallel doped regions and a plurality of generally parallel metalized regions is of the metal-on-semiconductor junction type. 
     
     
       19. The storage device of  claim 17 , wherein said rectifying conductive means between said plurality of generally parallel doped regions and a plurality of generally parallel metalized regions is of the p-n junction type. 
     
     
       20. The storage device of  claim 14 , wherein one of said plurality of generally parallel conductive means is a plurality of generally parallel metalized regions. 
     
     
       21. The storage device of  claim 14 , wherein said rectifying conductive means is comprised by a transistor as the base-emitter junction. 
     
     
       22. The storage device of  claim 14 , further comprising means for retaining the address of the information to be accessed. 
     
     
       23. The storage device of  claim 22 , further comprising means for incrementing the retained address. 
     
     
       24. The storage device of  claim 22 , further comprising means for setting the retained address. 
     
     
       25. An electronic information storage device comprising a plurality of storage means where each storage means comprises:
 a plurality of generally parallel conductive means;   a second plurality of generally parallel conductive means that is generally perpendicular to and overlapping with the first said plurality of generally parallel conductive means;   a plurality of bits of potential information storage where a bit of said plurality of bits is present in the general vicinity of each point of intersection of each conductive means of the first said plurality of generally parallel conductive means and each conductive means of the second said plurality of generally parallel conductive means, and where the state of any said bit is determined by the presence or absence of a rectifying conductive means at each said general vicinity of said point of intersection;   means for selecting a conductive means of one plurality of generally parallel conductive means, and means for biasing the generally parallel conductive means of the other plurality of generally parallel conductive means such that each said rectifying conductive means present between a conductive means of said biased plurality of generally parallel conductive means and a conductive means of the other said plurality of generally parallel conductive means is potentially forward biased; and   means for selecting a biased conductive means by electronically disabling conductive means within said biased plurality of generally parallel conductive means by shifting the voltage of those biased conductive means that are to be disabled;   where at least one of said plurality of generally parallel conductive means is common to more than one said storage means.   
     
     
       26. The storage device of  claim 25 , wherein said means for selecting a conductive means of one plurality of generally parallel conductive means comprises:
 means for biasing the generally parallel conductive means of the said one plurality of generally parallel conductive means such that each said rectifying conductive means present between a conductive means of said biased plurality of generally parallel conductive means and a conductive means of the other said plurality of generally parallel conductive means is potentially forward biased; and   means for selecting a biased conductive means by electronically disabling conductive means within said biased plurality of generally parallel conductive means by shifting the voltage of those biased conductive means that are to be disabled.   
     
     
       27. A semiconductor information storage device comprising:
 a plurality of generally parallel conductive means;   a second plurality of generally parallel conductive means that is generally perpendicular to and overlapping with the first said plurality of generally parallel conductive means where one of said two pluralities of generally parallel conductive means is generally a surface layer of the semiconductor; and   a plurality of bits of potential information storage where a bit of said plurality of bits is present in the general vicinity of each point of intersection of each conductive means of the first said plurality of generally parallel conductive means and each conductive means of the second said plurality of generally parallel conductive means, and where the state of any said bit is determined by the presence or absence of a rectifying conductive means at each said general vicinity of said point of intersection, and where any said presence or absence of a rectifying conductive means is determined by the leaving in place or the removal, respectively, of a portion of the surface layer conductive means.   
     
     
       28. An electronic array of selectable points comprising:
 a plurality of conductive means;   a second plurality of conductive means;   a plurality of selectable points where a point of said plurality of selectable points is present in the general vicinity of each point of intersection of each conductive means of the first said plurality of conductive means and each conductive means of the second said plurality of conductive means;   means for selecting a conductive means of one plurality of conductive means, and means for biasing the conductive means of the other plurality of conductive means such that each said selectable point present between a conductive means of said biased plurality of conductive means and a conductive means of the other said plurality of conductive means is potentially forward biased; and   means for selecting a biased conductive means by electronically disabling conductive means within said biased plurality of conductive means by shifting the voltage of those biased conductive means that are to be disabled.   
     
     
       29. The electronic array of selectable points of  claim 28 , wherein said means for selecting a conductive means of one plurality of generally parallel conductive means comprises:
 means for biasing the conductive means of the said one plurality of conductive means such that each said selectable point present between a conductive means of said biased plurality of conductive means and a conductive means of the other said plurality of conductive means is potentially forward biased; and   means for selecting a biased conductive means by electronically disabling conductive means within said biased plurality of conductive means by shifting the voltage of those biased conductive means that are to be disabled.   
     
     
       30. The electronic array of selectable points of  claim 28 , wherein said each selectable point comprises a light emitting diode (LED) which will emit light when forward biased. 
     
     
       31. An information-storage circuit, the circuit comprising:
 a plurality of row storage lines;   a plurality of column storage lines overlapping the plurality of row storage lines;   a plurality of storage locations, wherein each storage location is disposed proximate to a point of intersection between a row storage line and a column storage line;   a plurality of nonlinear storage elements, wherein each nonlinear storage element is disposed at a storage location;   a plurality of row decoder lines electrically connected to the plurality of row storage lines;   a plurality of column decoder lines electrically connected to the plurality of column storage lines;   a plurality of nonlinear row address elements connected to the plurality of row decoder lines;   a plurality of nonlinear column address elements connected to the plurality of column decoder lines;   a plurality of row address lines connected to the plurality of nonlinear row address elements, wherein a number of the row address lines is less than a number of the row decoder lines;   a plurality of column address lines connected to the plurality of nonlinear column address elements, wherein a number of the column address lines is less than a number of the column decoder lines;   wherein a row address applied to the plurality of row address lines causes the plurality of nonlinear row address elements to select a row decoder line, the selected row decoder line selects a row storage line to which it is connected, a column address applied to the plurality of column address lines causes the plurality of nonlinear column address elements to select a column decoder line, the selected column decoder line selects a column storage line to which it is connected, and the intersection between the selected row storage line and the selected column storage line comprises the storage location defined by the row address and the column address.    
     
     
       32. The information-storage circuit of claim 31, wherein each of the plurality of nonlinear storage elements comprises a diode.  
     
     
       33. The information-storage circuit of claim 31, wherein each of the plurality of nonlinear row address elements comprises a diode.  
     
     
       34. The information-storage circuit of claim 31, wherein each of the plurality of nonlinear column address elements comprises a diode.  
     
     
       35. The information-storage circuit of claim 31, wherein at least one storage location is programmed with data comprising at least one of music, video, computer software, a computer application, reference data, text, or a diagram.  
     
     
       36. The information-storage circuit of claim 31, further comprising logic circuitry connected to the plurality of column address lines configured to apply a plurality of column addresses to the plurality of column address lines simultaneously.  
     
     
       37. The information-storage circuit of claim 31, further comprising logic circuitry connected to the plurality of column address lines configured to substantially halt the flow of electrical current to at least one of the plurality of column address lines.  
     
     
       38. The information-storage circuit of claim 31, wherein the circuit is disposed within a removable memory storage device.  
     
     
       39. The information-storage circuit of claim 31, further comprising counter circuitry connected to at least one of the plurality of row address lines or the plurality of column address lines.  
     
     
       40. The information-storage circuit of claim 31, further comprising shift register circuitry connected to at least one of the plurality of row address lines or the plurality of column address lines.  
     
     
       41. The information-storage circuit of claim 40, further comprising counter circuitry connected to and disposed between the shift register circuitry and at least one of the plurality of row address lines or the plurality of column address lines.  
     
     
       42. The information-storage circuit of claim 41, wherein the shift register circuitry loads a row address into the counter circuitry, and the counter circuitry applies the row address to at least one of the plurality of row address lines.  
     
     
       43. The information-storage circuit of claim 31, wherein each of the plurality of nonlinear storage elements comprises a programmable material.  
     
     
       44. The information-storage circuit of claim 43, wherein said programmable material comprises a fusible link.  
     
     
       45. The information-storage circuit of claim 43, wherein said programmable material comprises a charge-storage material.  
     
     
       46. The information-storage circuit of claim 31, wherein a center-to-center distance between the nonlinear storage elements is less than approximately 0.45 microns.  
     
     
       47. The information-storage circuit of claim 31, further comprising, disposed around the plurality of storage locations,
 a package configured to interface with an electronic device.    
     
     
       48. The information-storage device of claim 47, further comprising interface logic circuitry connected to at least one of the plurality of row storage lines or the plurality of column storage lines.  
     
     
       49. The information-storage device of claim 47, wherein the package is connected to an electronic device selected from the group consisting of a computer, a microprocessor, a microcomputer chip, and a digital logic device.  
     
     
       50. The information-storage circuit of claim 47, wherein at least one storage location is programmed with data comprising at least one of music, video, computer software, a computer application, reference data, text, or a diagram.  
     
     
       51. The information-storage device of claim 47, wherein the package is removable and interchangeable to the electronic device.  
     
     
       52. The information-storage device of claim 51, further comprising interface logic circuitry connected to at least one of the plurality of row storage lines or the plurality of column storage lines, wherein at least one storage location is programmed with data comprising at least one of music, video, computer software, a computer application, reference data, text, or a diagram.