Method for compensating non-linearity of a sigma-delta analog-to-digital converter

Abstract

The invention concerns a method for compensating the non-linearity of a sigma-delta analog-to-digital converter (A 2 ) with quantization at N levels comprising a digital-to-analog converter ( 24 ). The method comprises a calibrating step which consists in transforming the multibit sigma-delta analog-to-digital converter (A 2 ) into a sigma-delta analog-to-digital converter with quantization at three levels, then at two levels. The correction values of each level to be corrected are accurately measured. The method also comprises a normal functioning phase which consists, when the sigma-delta an analog-to-digital converter (A 2 ) is operating with quantization at N levels, in producing an instantaneous correction of errors of the analog-to-digital converter ( 24 ) using said correction values.

1. A method of compensating the non-linearity of a sigma-delta analog-to-digital converter with a quantizer having N quantizing levels, and including a digital-to-analog converter in a feedback loop, comprising:
 a normal operation phase in which a plurality of digital values corresponding to a plurality of quantizing levels are modified by correction values C i , where i is a positive integer from 1 to N−2; and 
 a calibration phase in which the correction values C i  are calculated from values of the output of the quantizer of the sigma-delta analog-to-digital converter processed digitally with the digital-to-analog converter retained in the feedback loop of the sigma-delta analog-to-digital converter and after converting the multibit sigma-delta analog-to-digital converter into a sigma-delta analog-to-digital converter with three quantizing levels; 
 wherein during the calibration phase the multibit sigma-delta analog-to-digital converter is converted into a sigma-delta analog-to-digital converter with three quantizing levels X m , X M , and X i , where i is from 1 to N−2; 
 wherein, during a period P 1   i  of the calibration phase, a predetermined value is delivered to the input of the sigma-delta analog-to-digital converter and the values from the output of the quantizer of the sigma-delta analog-to-digital converter are processed digitally; 
 wherein the calibration phase is executed N−2 times, retaining the levels X m  and X M , and taking successively for the level X i , the N−2 levels other than the levels X m  and X M ; and 
 wherein the correction values C i  of the N−2 levels other than X m  and X M  are calculated using a sum of the processed values, the N−2 correction values C i  being adapted to modify the N−2 levels other than X m  and X M  during the normal operation phase. 
 
     
     
       2. The method of  claim 1 , further comprising during the calibration phase and before calculating the correction values C i , at least one step F during which the multibit sigma-delta analog-to-digital converter is converted into a sigma-delta analog-to-digital converter with two quantizing levels X m  and X M , during a period P 2 , wherein the predetermined value is delivered to the input of the sigma-delta analog-to-digital converter and the successive values of the output of the sigma-delta analog-to-digital converter are processed digitally. 
     
     
       3. The method of  claim 2 , wherein the sigma-delta analog-to-digital converter with N quantizing levels is converted into a sigma-delta analog-to-digital converter with a number of quantizing levels less than N by modifying quantizing threshold values and by digital processing using internal comparators. 
     
     
       4. The method of  claim 3 , wherein during the normal operation phase, the correction value C i  is added to each level X i  present at the output of the quantizer. 
     
     
       5. The method of  claim 4 , wherein step F of the calibration phase is executed N−2 times, each time taking a period P 2   i  equal to each period P 1   i , and a sum S 2   i  is calculated of all the values leaving the sigma-delta analog-to-digital converter during each execution, after which a correction value C i  corresponding to the value X i  is calculated from the equation: C i =(S 2   i −S 1   i )/N i . 
     
     
       6. The method of  claim 5 , wherein the period P 1   i , for each level X i , is equal to the period needed to count the number N i  of values equal to X i  at the output of the sigma-delta analog-to-digital converter until the number N i  is equal to a given number N 0 . 
     
     
       7. The method of  claim 3 , wherein the predetermined value is equal to zero, and wherein during the calibration phase and during the period P i  for each level X i , the number N i  of values equal to X i  and the total number NT i  of all the output values are counted at the output of the sigma-delta analog-to-digital converter and a sum S 1   i  of the NT i  values is calculated. 
     
     
       8. The method of  claim 7 , wherein the period P 1   i , for each level X i , is equal to the period needed to count the number N i  of values equal to X i  at the output of the sigma-delta analog-to-digital converter until the number N i  is equal to a given number N 0 . 
     
     
       9. The method of  claim 3 , wherein the levels X m  and X M  are respectively the minimum value and the maximum value of the N quantizing levels. 
     
     
       10. The method of  claim 2 , wherein the levels X m  and X M  are respectively the minimum value and the maximum value of the N quantizing levels. 
     
     
       11. The method of  claim 2 , wherein during the normal operation phase, the correction value C i  is added to each level X i  present at the output of the quantizer. 
     
     
       12. The method of  claim 2 , wherein the predetermined value is equal to zero, and wherein during the calibration phase and during the period P 1   i  for each level X i , the number N i  of values equal to X i  and the total number NT i  of all the output values are counted at the output of the sigma-delta analog-to-digital converter and a sum S 1   i  of the NT i  values is calculated. 
     
     
       13. The method of  claim 1 , wherein the levels X m  and X M  are respectively the minimum value and the maximum value of the N quantizing levels. 
     
     
       14. The method of  claim 1 , wherein during the normal operation phase, the correction value C i  is added to each level X i  present at the output of the quantizer. 
     
     
       15. The method of  claim 1 , wherein the predetermined value is equal to zero, and wherein during the calibration phase and during the period P 1   i  for each level X i , the number N i  of values equal to X i  and the total number NT i  of all the output values are counted at the output of the sigma-delta analog-to-digital converter and a sum S 1   i  of the NT i  values is calculated. 
     
     
       16. A system for compensating the non-linearity of a sigma-delta analog-to-digital converter having a quantizer with N quantizing levels, comprising:
 a digital-to-analog converter in a feedback loop and a digital filter, wherein the digital-to-analog converter comprises means for calculating correction values C i , where i is a positive integer from 1 to N−2, during a calibration phase, and from values of the output of the quantizer of the sigma-delta analog-to-digital converter processed digitally with the digital-to-analog converter retained in the feedback loop of the sigma-delta analog-to-digital converter and by converting the multibit sigma-delta analog-to-digital converter into a sigma-delta analog-to-digital converter with three quantizing levels, and means for modifying a plurality of digital values corresponding to a plurality of quantizing levels by applying the correction values C i  during a normal operation phase; 
 wherein the calculating and modifying means comprise:
 counter means for counting the values leaving the quantizer of the sigma-delta analog-to-digital converter; 
 at least one accumulator for summing the values leaving the quantizer of the sigma-delta analog-to-digital converter; 
 storage means for memorizing numbers delivered by the counter means and the accumulator; 
 processor means for performing calculations on the memorized numbers and generating control signals in the system for controlling the various phases; 
 a correction module between the quantizer and the digital filter, communicating with the processor means; and 
 comparators and a digital processor module internal to the N-level quantizer and capable of converting the quantizer into a quantizer with fewer than N quantizing levels. 
 
 
     
     
       17. A method of compensating the non-linearity of a sigma-delta analog-to-digital converter with a quantizer having N quantizing levels and including a digital-to-analog converter in a feedback loop, comprising:
 a normal operation phase in which a plurality of digital values corresponding to a plurality of quantizing levels are modified by correction values C i , where i is a positive integer from 1 to N−2; and 
 a calibration phase in which the correction values C i  are calculated from values of the output of the quantizer of the sigma-delta analog-to-digital converter processed digitally with the digital-to-analog converter retained in the feedback loop of the sigma-delta analog-to-digital converter and after converting the multibit sigma-delta analog-to-digital converter into a sigma-delta analog-to-digital converter with three quantizing levels; 
 wherein during the calibration phase the multibit sigma-delta analog-to-digital converter is converted into a sigma-delta analog-to-digital converter with three quantizing levels X m , X M , and X i , where i is from 1 to N−2; 
 wherein, during a period P 1   i  of the calibration phase, a predetermined value is delivered to the input of the sigma-delta analog-to-digital converter and the values from the output of the quantizer of the sigma-delta analog-to-digital converter are processed digitally; 
 wherein the calibration phase is executed N−2 times, retaining the levels X m  and X M , and taking successively for the level X i , the N−2 levels other than the levels X m  and X M ; and 
 wherein the correction values C i  of the N−2 levels other than X m  and X M  are calculated using the processed values, the N−2 correction values C i  being adapted to modify the N−2 levels other than X m  and X M  during the normal operation phase. 
 
     
     
       18. The method of  claim 17 , further comprising during the calibration phase and before calculating the correction values C i , at least one step F during which the multibit sigma-delta analog-to-digital converter is converted into a sigma-delta analog-to-digital converter with two quantizing levels X m  and X M , during a period P 2 , wherein the predetermined value is delivered to the input of the sigma-delta analog-to-digital converter and the successive values of the output of the sigma-delta analog-to-digital converter are processed digitally. 
     
     
       19. A method of compensating the non-linearity of a sigma-delta analog-to-digital converter, the method comprising:
 during a normal operation phase:
 operating a quantizer with N quantizing levels; 
 generating a digital output value for each of the N quantizing levels, wherein the N quantizing levels include a minimum quantizing level X m , a maximum quantizing level X M , and N−2 remaining quantizing levels X i , where i is from 1 to N−2; and 
 modifying each of the digital output values that correspond to the N−2 remaining quantizing levels using a respective one of N−2 correction values generated during a first portion of a calibration phase that is executed N−2 times; 
   during the first portion of the calibration phase:
 digitally processing the digital output values with a digital-to-analog converter retained in a feedback loop of the sigma-delta analog-to-digital converter; 
 calculating each respective N−2 correction value using a first sum of the digitally processed digital output values; 
 operating the quantizer with three quantizing levels comprising X m , X M , and one of the remaining quantizing levels X i ; 
 providing a predetermined input value to the sigma-delta analog-to-digital converter; 
 retaining the levels X m  and X M , and taking successively for the level X i , the N−2 levels other than the levels X m  and X M ; and 
 calculating the correction values of the N−2 levels other than X m  and X M  using a sum of the processed values. 
   
     
     
       20. The method of claim 19, further comprising during a second portion of the calibration phase, operating the quantizer with two quantizing levels: X m  and X M . 
     
     
       21. The method of claim 20, wherein the quantizer is operated with a number of quantizing levels less than N by modifying internal quantizing threshold values and by performing said digital processing using comparator circuits internal to the quantizer. 
     
     
       22. The method of claim 20, further comprising executing the calibration phase N−2 times, wherein a time to execute the second portion of the calibration phase is substantially equal to a time to execute the first portion of the calibration phase, and wherein during the second portion, a second sum (S2 i ) is calculated from all of the digital output values during each execution, wherein each correction value (C i ) corresponding to each remaining quantizing level X i  is calculated by C i =(S2 i −S1 i )/N i , where N i  comprises a number of occurrences in which the digital output values are equal to X i . 
     
     
       23. The method of claim 22, wherein the time to execute the second portion of the calibration phase is substantially equal to the period used to count the number N i  until the number N i  is equal to the number N 0 . 
     
     
       24. The method of claim 19, wherein during the normal operation phase, said modifying includes adding the respective correction value to each digital output value corresponding to each remaining quantizing level X i . 
     
     
       25. The method of claim 19, wherein the predetermined input value is equal to zero, and wherein during the first portion of the calibration phase, for each remaining quantizing level X i , the number N i  of values equal to X i  and the total number NT i  of all the digital output values are counted and a first sum S1 i  of the NT i  values is calculated. 
     
     
       26. The method of claim 19, wherein during each of the N−2 executions of the first portion of the calibration phase, each of the respective correction values for the N−2 remaining quantizing levels is calculated using a first sum (S1 i ) of a number N 0  of the digital output values, where N 0  comprises a number of occurrences in a given period of time in which the digital output values are equal to X i . 
     
     
       27. A system for compensating the non-linearity of a sigma-delta analog-to-digital converter, the system comprising:
 a quantizer configured to operate in a normal operation phase and a first portion of a calibration phase, wherein the quantizer is configured to operate during the normal operation phase with a plurality of quantizing levels (N) including a minimum quantizing level X m , a maximum quantizing level X M , and N−2 remaining quantizing levels X i , where i is from 1 to N−2, wherein the quantizer is configured to output a plurality of digital output values, each digital output value corresponding to one of the plurality of quantizing levels, and wherein the quantizer is further configured to operate with three quantizing levels comprising X m , X M , and one of the remaining quantizing levels X i  during the first portion of the calibration phase that is executed N−2 times;   a digital-to-analog converter coupled in a feedback loop to the quantizer during the first portion of the calibration phase, wherein the digital-to-analog converter is configured to digitally process the plurality of digital output values, wherein during the first portion of the calibration phase, the plurality of digital output values of the quantizer are based on a predetermined input value;   a control device coupled to the quantizer and configured, during the first portion of the calibration phase, to retain the levels X m  and X M  and take successively for the level X i  the N−2 levels other than the levels X m  and X M , and to calculate a respective correction value from the plurality of digital output values for each of the digital output values that corresponds to the N−2 remaining quantizing levels; and   a corrector module coupled to the quantizer, wherein the corrector module is configured, during the normal operation phase, to modify each of the digital output values that corresponds to the N−2 remaining quantizing levels using a respective one of the N−2 correction values.   
     
     
       28. The system of claim 27, wherein the control device comprises:
 a counter circuit configured to count ones of the plurality of output digital values of the quantizer;   an accumulator configured to sum the plurality of output digital values of the quantizer;   storage device coupled to the counter circuit and to the accumulator, wherein the storage device is configured to store values provided by the counter circuit and the accumulator; and   a processor module coupled to the storage device and configured to perform calculations on the values stored within the storage device and to generate control signals for controlling the quantizer.   
     
     
       29. The system of claim 28, wherein the quantizer includes a comparator circuit coupled to a processor module, wherein the quantizer is configured to operate with fewer than N quantizing levels depending upon the control signals. 
     
     
       30. The system of claim 27, wherein during each of the N−2 executions of the first portion of the calibration phase, the control device is further configured to calculate each of the respective correction values for the N−2 remaining quantizing levels using a first sum (S1 i ) of a number N 0  of the digital output values, where N 0  comprises a number of occurrences in a given period of time in which the digital output values are equal to X i . 
     
     
       31. The method of claim 30, wherein the quantizer is further configured to operate with two quantizing levels: X m  and X M  during a second portion of the calibration phase. 
     
     
       32. A system for compensating the non-linearity of a sigma-delta analog-to-digital converter, the system comprising:
 a quantizer configured to operate in a normal operation phase and a first portion of a calibration phase, wherein the quantizer is configured to operate during the normal operation phase with a plurality of quantizing levels (N) and to generate a digital output value for each of the N quantizing levels, wherein the N quantizing levels include a minimum quantizing level X m , a maximum quantizing level X M , and N−2 remaining quantizing levels X i , where i is from 1 to N−2, and wherein the quantizer is further configured to operate with three quantizing levels comprising X m , X M , and one of the remaining quantizing levels X i  during the first portion of the calibration phase that is executed N−2 times;   a digital-to-analog converter coupled in a feedback loop to the quantizer during the first portion of the calibration phase;   means for retaining the levels X m  and X M  and for taking successively for the level X i  the N−2 levels;   means for calculating, during the first portion of the calibration phase, a respective correction value from the plurality of digital output values for each of the digital output values that corresponds to the N−2 remaining quantizing levels, wherein the digital output values are processed digitally by the digital-to-analog converter retained in the feedback loop of the sigma-delta analog-to-digital converter;   wherein the means for calculating comprises:
 counter means for counting specific ones of the digital output values of the quantizer; 
 at least one accumulator for summing the digital output values of the quantizer; 
 storage means for storing numbers delivered by the counting means and the at least one accumulator; and 
 processor means for performing calculations on the stored numbers and generating control signals for controlling the quantizer; and 
 means for modifying, during the normal operation phase, each of the digital output values that correspond to the N−2 remaining quantizing levels using a respective one of the N−2 correction values; 
 wherein the means for modifying comprises:
 a correction module coupled between the quantizer and a digital filter, wherein the correction module communicates with the processor means; and 
 within the quantizer, a comparator circuit and a digital processor module are configured to operate the quantizer with fewer than N quantizing levels. 
 
   
     
     
       33. The system of claim 32, wherein during each of the N−2 executions of the first portion of the calibration phase, the means for calculating is further configured to calculate each of the respective correction values for the N−2 remaining quantizing levels using a first sum (S1 i ) of a number N 0  of the digital output values, where N 0  comprises a number of occurrences in a given period of time in which the digital output values are equal to X i . 
     
     
       34. The method of claim 33, wherein during a second portion of the calibration phase, the quantizer is further configured to operate with two quantizing levels: X m  and X M . 
     
     
       35. The method of claim 32, wherein the digital output values are based on a predetermined value provided to an input of the sigma-delta analog-to-digital converter.